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Fri, 10 Jul 2009 13:17:06 -0500 |
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Jack,
We have a set of ICT standards we work with specifying TP clearances,
quantities, etc. that we design to. We also have our ICT developers import
the data and give it a quick look before we order any PCBs - this is real
easy as most test development tools have quick auditing routines for probe
locations.
We use specific TP vias and testprep, all other vias are soldermask
encroached as you mention.
Hth,
Dave
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