Inge,
....have nothing myself
at the moment——how about that skull to 'skoal' with?
werner
-----Original Message-----
From: Inge <[log in to unmask]>
To: TechNet E-Mail Forum <[log in to unmask]>; [log in to unmask]
Sent: Fri, 29 May 2009 10:20 am
Subject: Re: [TN] Looking for opinions on separation/delamination between copper land and dielectric material.
........> How to improve on that? EASY, do not do T-shock in production
[slow cooling rate after reflow to 1.5C/sec or less] and in testing go less
severe or no T-shock at all.
>
Exactly what I pointed at in a recent message. The most dangerous moment for
a electronic product is in the manufacturing line! Good to hear guru W
underline that.
Looking forward to the TN Friday light entertainments....have nothing myself
at the moment
Inge
----- Original Message -----
From: "Werner Engelmaier /*" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, May 29, 2009 2:43 PM
Subject: Re: [TN] Looking for opinions on separation/delamination between
copper land and dielectric material.
> Ni hao charming,
> That separation can occur during cooling from solder reflow [if too
> fast=thermal shock] or in your T-shock test [would have been good to give
> details.
> Your TSSOP leads are likely Alloy42 [=very stiff] and are very stubby
> [=very stiff] with SAC-solder [=very stif
f].
> In T-shock it is NOT any CTE-mismatch that causes your problem [even
> though it does not help, and may cause reliability problems with the
> product], but the thermal gradients resulting from T-shock and causing
> component/PCB warpage.
>
> How to improve on that? EASY, do not do T-shock in production [slow
> cooling rate after reflow to 1.5C/sec or less] and in testing go less
> severe or no T-shock at all.
>
> Werner
>
>
>
>
>
>
>
>
>
> -----Original Message-----
> From: Charming Chan <[log in to unmask]>
> To: [log in to unmask]
> Sent: Fri, 29 May 2009 4:45 am
> Subject: [TN] Looking for opinions on separation/delamination between
> copper land and dielectric material.
>
>
>
>
>
>
>
>
>
>
> Hello All,
>
> Our guys ran a thermal shock test to verify solder joint reliability of a
> TSSOP component. The micro-section shows that there is a minor crack at
> the
> toe side of the solder joint and a separation(delamination) between the
> copper land and the dielectric material.
>
> My question is,
>
> Where did the separation/delamination occur? PCB fab house, PCB assembly
> house, or thermal shock test?
>
> If the separation/delamination occurred at pcb fab house, then, what's the
> possible root cause gonna be?
>
> If the separation/delamination occurred at thermal shock test or pcb
> assembly house, then, is it caused by CTE mismatch between pcb base
> material, solder alloy, and gull-wing footprint? How to improve on that?
>
> Brain storm, and any input is appreciated.
> I will get the micro-section picture posted once I get it. Thank you all.
>
> Best Regards
> Charming Chan
>
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