Was the sample preconditioned (pre-baked)?
What temp solder?
Microsection sample dwell time on solder?


"Where did the separation/delamination occur? PCB fab house, PCB assembly
house, or thermal shock test?"

Do you require your pwb supplier to do any sample solder floats prior 
to shipping to you as part of their standard lot acceptance?
    * Break the problem down.
    * Test a bare pwb yourself and examine x-section.
    * Examine a x-section of an assembled board after your solder 
process (without any additional solder shock)


At 01:45 AM 5/29/2009, Charming Chan wrote:
>Hello All,
>
>Our guys ran a thermal shock test to verify solder joint reliability of a
>TSSOP component. The micro-section shows that there is a minor crack at the
>toe side of the solder joint and a separation(delamination) between the
>copper land and the dielectric material.
>
>My question is,
>
>Where did the separation/delamination occur? PCB fab house, PCB assembly
>house, or thermal shock test?
>
>If the separation/delamination occurred at pcb fab house, then, what's the
>possible root cause gonna be?
>
>If the separation/delamination occurred at thermal shock test or pcb
>assembly house, then, is it caused by CTE mismatch between pcb base
>material, solder alloy, and gull-wing footprint? How to improve on that?
>
>Brain storm, and any input is appreciated.
>I will get the micro-section picture posted once I get it. Thank you all.
>
>Best Regards
>Charming Chan
>
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