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May 2009

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TechNet E-Mail Forum <[log in to unmask]>, Inge <[log in to unmask]>
Date:
Thu, 14 May 2009 21:26:36 +0200
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When this topic was actual, I plowed through lots of papers about dielectric 
issues. I still have a fat map filled with articles. Now, in my profession 
you must be a sceptic, so I found that this must be a parallel to surface 
induced charges in the passivation on MOS chips and other semis. Such 
charges can shift the state of the gates, and possibly damage some channels 
on MESFETs or HBTs. In my opinion, PWBs have far from the same possibility 
to charge, the dielectric insulation for PWBs are magnitudes from the high 
dielectric of semis.
Furthermore, if you want 'discharge' your board before mounting, just dip 
them in for a second in ionized water and rinse in deionized ditto. I don't 
dare use the word nonsence about charges on bare boards, but maybe low risk 
matter. Very low. But don't refer to me only, I have limited experience as 
well as most of us.

Well, there may be one exception: Teflon boards, which I've not tested.

Inge

PS. Charges are easily checked with a simple ESD meter.


----- Original Message ----- 
From: "Robert Kondner" <[log in to unmask]>
To: "'TechNet E-Mail Forum'" <[log in to unmask]>; "'Inge'" 
<[log in to unmask]>
Sent: Thursday, May 14, 2009 9:03 PM
Subject: RE: [TN] Bare PCB Packaging Requirements


> Inge,
>
>  Is Electric Field really the issue or is it more of a case of induced
> currents?
>
>  If I rub a piece of plastic with wool so It has a very high field, and if
> I then set an IC on that plastic, will any current flow anywhere?
>
>  If not then I do not see how the IC can be damaged.
>
>  If I take a 1.5 volt battery and connect it to power and signal pins will
> current flow? I think so and the part will probably be destroyed.
>
> So is it field or induced current levels?
>
> Thanks,
> Bob Kondner
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Inge
> Sent: Thursday, May 14, 2009 2:49 PM
> To: [log in to unmask]
> Subject: Re: [TN] Bare PCB Packaging Requirements
>
> Electrostatic fields can be induced in high dielectrics and once there, 
> may
> be hard to get rid of. As little as 50 VDC can be a problem for IC chips
> without enough I/O diode protections. We have had some issues which might
> have been caused by such surface charges, but we could never prove it. To 
> be
>
> sure , we demand ESD safe bags. Additional cost negligible.
> Inge
>
> ----- Original Message ----- 
> From: "John Parsons" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Thursday, May 14, 2009 8:36 PM
> Subject: [TN] Bare PCB Packaging Requirements
>
>
>> Tell us, how many CEM's out there are demanding that bare PCB's be
>> received
>> in vacuum sealed moisture barrier anti-static bags.  If so, what is your
>> reasoning?  Just to be clear my focus here is "anti-static" not the
>> moisture
>> barrier properties of the packaging.
>>
>>
>>
>> Regards
>>
>>
>>
>> John Parsons
>>
>>
>>
>>
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