Absolutely correct, Anil. Approaching the point where the flux removal
rate d/dx roughly equals zero, very little flux or polar contaminants
are being removed with respect to time in the wash. You may need it to
be cleaner, but leaving it in the wash may not be the answer, as you
reach a point where the maximum capability of the wash is reached.
But that does not mean the residues are completely washed away, they are
simply entrapped. Even if it is no-clean this can be the result in an
environment where moisture is allowed to condense or nearly condense,
and power is applied.
Isn't it worse with an ORH0 flux?
Absolutely, except that it is far easier to clean an ORH0 flux, and
validate the process capability for cleanliness, and thus less likely to
happen.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Anil kher
Sent: Wednesday, May 27, 2009 2:25 PM
To: [log in to unmask]
Subject: Re: [TN] humidity test failure
Condensation
Maintaining 90% RH is a challenge and it is impossible to prevent
condensation. I would suggest we study the psychrometric charts closely.
To
begin the room RH has to be below 50%. And temp control within 1deg F.
And
completely insulated from an air swish. I hv forgotten the d/dx 30 yrs
ago.
But practically testing at high Rh is cool if yr ambient is 40%. Above
that
yr are likely to get condensation.
Well the matter we see in the photos comes from somewhere - condensation
and
Voltage have accelerated it.- and not from the PCB - cause any pcb made
in a
normal shop will pass SIR post etch and stay that way.
It's the flux. And for such a low profile component u need a good
washing
machine. Maybe ultrasonic - or lots of hot water and sonics and air
agitation.
Its finally d/dx. The cleaner you need the longer and harder u need to
clean.
Best wishes
Anil
-----Original Message-----
From: Inge [mailto:[log in to unmask]]
Sent: Wednesday, May 27, 2009 22:32
Subject: Re: humidity test failure
We had an awful lot of environmental test chambers, and we followed
MIL-STD
like a blind klinging to his stick. With time, we have realized the
questionable relationship between those tests and the unpredictable
mother
Nature. The exact repetition of temperature up, temp down, dwell, temp
down
etc does not always correspond to the erratic reality with endless
variations and combinations of condensation and vibration, heat and
salt,
power switching and deep freeze, sun irradiation and sand blast , very
short
exposure followed by extremly long one etc etc. I listened to a guy who
was
a successful design manager, whose motto was 'skip all testing, do the
right
design or process from the beginning' . Easy said, but still interesting
topic. Am brought up with MIL-STD, so I'm little ambivalent, but I try
to
think like him. And, in fact, with all billion hours of testing
everything
on this planet, should we not have background enough for avoiding all
disasters..like corroded ceramic caps, for instance. Why do we repeat
all
failures that have been known for decades?
Inge
----- Original Message -----
From: "Chris Mahanna" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, May 27, 2009 6:34 PM
Subject: Re: [TN] humidity test failure
Hi Wayne,
Agreed. The DUT probably slipped close to, or below dew. Close can be
just
as bad. And, surely there is trapped ionics. But, I suspect a
correlation
ranking might show those non-wetted solderable surfaces as your real
culprit.
Ability to control the chamber and DUT is highly dependent on absolute
humidity. 85/85 is very tough. Anything higher is crazy. The common
25-65C, 90% is quite difficult without good multi loop control. If
you're
cycling a heavy assembly you will probably want to use the surface temp
as
an input to your controller.
IPC-9201A is a good source of info. NPL has several papers.
Fully processed comb patterns can 'survive' 85/85 or 25-65/90 SIR/ECM
tests
for 1000 hours without cc, but it's not easy.
Chris
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Thayer, Wayne
Sent: Tuesday, May 26, 2009 10:01 PM
To: [log in to unmask]
Subject: [TN] humidity test failure
Hi Technet Gurus!
I have attached a picture of a part responsible for excess current draw
during an extended humidity/temperature cycling test. (I copied Steve so
he
can hopefully post!)
The board was carefully solvent cleaned, but no SIR test validating the
process strips all ionic contamination. The board is in an enclosure
where
plenty of ionic contaminants are available.
Humidity was supposed to not exceed 90% and was to be non-condensing
during
cycling. There were a handful of components which displayed similar
deposits on the same circuit board. These were the only parts biased
during
the humidity test. I believe the evidence suggests at least some
condensation occurred. To me the deposits look like salts. But what
do
"the experts" think?
Is there any rule of thumb as to humidity levels where we are nuts to
try to
survive without conformal coating? Part of the adjacent circuitry
contains
RF devices and those guys get panic-stricken when told we probably need
to
conformal coat!
Wayne Thayer
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