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Subject:
From:
Dee Stover <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Dee Stover <[log in to unmask]>
Date:
Mon, 6 Apr 2009 14:16:52 -0700
Content-Type:
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Just like the tax code, subject to interpretation.   Holes that are 
subject to soldering, to me, are holes with leads in them.  I now 
believe all vias can be direct connect based on section IPC-2221A 
9.1.3 & IPC-A-610B section 4.2.4.
"When solder has not wetted side of holes, it should be considered a 
process indicator as per J-STD-001. There is no nonconforming defect 
condition for this."



At 12:06 PM 4/6/2009, you wrote:
>Try  IPC-2221A 9.1.3 The first sentance pretty much says what you said..
>
>Allen Maddox, CID+
>
>Allen Maddox Printed Circuit Board Designs and Services
><http://www.maddoxpcb.com/>www.maddoxpcb.com
>http://www.linkedin.com/in/trailsitter
>
>
>
>[]
>
>
>
>
>From: Dee Stover <[log in to unmask]>
>To: [log in to unmask]
>Sent: Monday, April 6, 2009 2:58:40 PM
>Subject: [DC] when do vias require a thermal relief
>
>Where in IPC does it specify when a via connected to a plane must 
>have thermal relief as opposed to direct connect?
>
>I would think it would have more to do with the assembly process 
>than the fabrication process.  For instance - wave, dip or drag soldering.
>
>You input is appreciated.
>
>Thanks,
>
>:-) Dee Stover  <mailto:[log in to unmask]>[log in to unmask]    x8489
>Tech Associate II
>National Optical Astronomy Observatories
><http://www.noao.edu/>www.noao.edu
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:-) Dee Stover  [log in to unmask]    x8489
Tech Associate II
National Optical Astronomy Observatories
www.noao.edu 

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