I read the package info and found it disturbing in that it indicates gold plating for the lead finish. This is an expensive option, so hopefully they didn't do it. BUT, if they did, and the gold on the bottom of the leads is as thick as that required for reliable production wirebonding (>30micro-inches), then there will likely be some nasty intermetallic issues when soldering this thing down: QFNs use very little solder, and that much gold in the joint will result in an increased reflow temperature as the solder attempts to dissolve the gold.
Lots of manufacturers do that--most infamous are producers of ceramic packages with wirebonding on the inside. The manufacturers are too cheap to pay for the masking step required to limit the amount of gold on the soldered connections. In order to use such parts, they must be solder dipped to eliminate the gold, and with QFNs with a large thermal pad, the solder must be wicked off or that pad will end up with way too much solder.
Note that the multi-row QFN is the same as an LGA pattern which was recently discussed on this forum--that thread contains more tips on reliability of using these devices.
Wayne Thayer
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Stadem, Richard D.
Sent: Wednesday, April 29, 2009 4:12 PM
To: [log in to unmask]
Subject: Re: [TN] Actel QFN180 Assembly
Yes, Steve, I have, outside of GD. It is not fun, very frustrating. The only tip I can give you is to try using some Kapton tape to experiment with the aperture openings until you think you have what you need, then remember to account for the one mil thicker deposit on account of the tape. Hopefully the next iteration will be the last.
However, I also had so many issues with the exposed copper on the edges of many of the QFNs and the unevenness and the huge delta CTE issues that I just decided it was not worth it to screw around with it anymore.
Here at GD we do not use QFN packages, we repackage them. We also work with the component manufacturer to give us the part in a different package.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Steve Gregory
Sent: Wednesday, April 29, 2009 2:32 PM
To: [log in to unmask]
Subject: Re: [TN] Actel QFN180 Assembly
Hi Jim,
Just having issues trying to find the right balance between the thermal pad and I/O pad opening dimensions in the stencil. We're about to go on our third stencil iteration and have a good idea what we're going to do, but it's frustrating when you follow the design guidelines that the manufacturer of the device say to do, and they don't work.
But why should I be surprised at that? Sheesh...
Just wondering if others go through this drill too?
Steve
-----Original Message-----
From: Jim Wolvansky [mailto:[log in to unmask]]
Sent: Wednesday, April 29, 2009 12:23 PM
To: Steve Gregory
Subject: RE: [TN] Actel QFN180 Assembly
Hello, Steve.
I've got some experience with devices like these, what issues are you having?
- Jim
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Steve Gregory
Sent: Wednesday, April 29, 2009 9:11 AM
To: [log in to unmask]
Subject: [TN] Actel QFN180 Assembly
Hi All,
We just ran a board with an Actel QFN180 device, and followed the stencil guidelines recommended by Actel in their publication:
http://www.actel.com/documents/QFN_AN.pdf
but we have had our issues.
I was wondering if anyone else has used this component and would be willing to share their experience with it.
We'll figure out things eventually, but I figure it wouldn't hurt to ask for some advice from this wonderful group.
Thanks,
Steve
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