Yes, it was my mistake. I intended to say dry-film tenting of vias on both
sides.
I have IPC-4761, and it basically covers an LPI tented via as Type I. What
is not clear is if by inclusion in the specification that this is a
preferred format or not, or was simply included because it is common
practice, right or wrong. In section 3.2 there is also a statement
"Plugging of vias from both sides of the hole results in manufacturability
and reliability issues".
I have heard warnings that tenting both sides can be problematic in that if
the seal is not perfect or somehow compromised (adhesion loss / puncture)
moisture or other contaminants can make their way in and the results can be
more catastrophic then a blind or single-side-tented via. I have also been
warned that at one time LPI tenting was "verboten" in MIL-STD-2000, so that
alone is questionable whether it was a scientifically derived requirement,
as some of the old requirements did not have the benefit of today's
research.
Thanks,
Kevin
-----Original Message-----
From: Chris Mahanna [mailto:[log in to unmask]]
Sent: Monday, April 13, 2009 1:25 PM
To: TechNet E-Mail Forum; Kevin Glidden
Subject: RE: [TN] Info on LPI tenting of vias, both sides
Kevin,
Generally LPI and Tent don't go in the same sentence unless there is a
secondary cover.
Is your intent via protection? Does your solderable final finish process
follow the mask?
Chris
Chris Mahanna
Robisan Laboratory Inc.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Kevin Glidden
Sent: Monday, April 13, 2009 12:45 PM
To: [log in to unmask]
Subject: [TN] Info on LPI tenting of vias, both sides
Hello everyone,
I am looking for information on the potential pitfalls of using LPI via
tenting on both sides, leaving an air pocket in the vias. Application is
NOT Pb-Free.
I located this article description, and wanted to see if anyone had it, but
other information, inputs, or articles are also welcome:
Title: An Evaluation of Via Hole Tenting with Solder Mask Designed to Pass
MIL-P-55110D Thermal Shock Requirements
Author(s): J.J. Davignon, F. Gray
Journal: <http://www.emeraldinsight.com/0305-6120.htm> Circuit World
Thanks!
---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 15.0 To
unsubscribe, send a message to [log in to unmask] with following text in the
BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or
(re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet
NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send
e-mail to [log in to unmask]: SET Technet Digest Search the archives of
previous posts at: http://listserv.ipc.org/archives Please visit IPC web
site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional
information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100
ext.2815
-----------------------------------------------------
---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 15.0
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
-----------------------------------------------------
|
