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From:
Joyce Koo <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Joyce Koo <[log in to unmask]>
Date:
Tue, 31 Mar 2009 20:12:19 -0400
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Does your estimate containing 25 percent allowable voids in bga? I'll keep my mouth shut and let werner go for big money :-). A lot more! 

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Sent using BlackBerry 





________________________________



From: Nieznanski, John A - SSD <[log in to unmask]> 

To: [log in to unmask] <[log in to unmask]>; [log in to unmask] <[log in to unmask]>; Joyce Koo 

Sent: Tue Mar 31 16:35:13 2009

Subject: RE: [TN] solder fatigue predictions for highly asymmetrical duty cycles 





Werner and Joyce, 



 



Thanks for the prompt feedback. My responses are below your questions.



 



John N.



 



 



________________________________



From: [log in to unmask] [mailto:[log in to unmask]] 

Sent: Monday, March 30, 2009 5:03 PM

To: [log in to unmask]; Nieznanski, John A - SSD; [log in to unmask]

Subject: Re: [TN] solder fatigue predictions for highly asymmetrical duty cycles



 



Hi Joyce & John,

Let's not be too hasty with a categorical NO--the real answer is: [drum roll] 'It depends.'



First, what does 'valid' mean. It needs to be understood that any reliability prediction is just an estimate of the outcome. This varies by the accuracy of quantifying the cyclic load conditions [geometry, physical properties, temperatures, time, etc.] which in most cases are approximations and median values.



 



             “Valid” in this general context means “useful for predicting or comparing outcomes, either analytical or experimental”. This leaves the door open for either a qualitative / comparative analysis or a quantitative analysis between alternative implementations.  The alternatives can be different hardware configurations or different usage scenarios (thermal environments, duty cycles). I agree and understand that the standard disclaimers apply, my mileage may vary, and that any TechNet offer is not “valid” where prohibited by law! ;-) However in this case, all the primary analysis parameters are known with reasonably good accuracy.  The uncertainty is in the accuracy and applicability of the analysis method. Obviously, empirical data obtained by testing would be best for correlating predictions with results.





Second, what is the purpose of the exercise. Are you comparing the projected reliability relative to some other set of inputs? That can be done validly with some insights of what is going on and what is important.



 



            More specifically and to the point for this discussion, the purpose of this exercise is to attempt to quantify the “estimated” solder joint reliability (probability of failure) for each SMT leaded and leadless component after a defined number of thermal cycles in specific thermal environments. Is it 10%, 1%, 0.1% or 0.01%? The thermal environments and thermal cycles are not uniform, but have known thermal limits, known durations and known duty cycles. All the components, geometries, component temperatures, circuit board temperatures, and material properties are also known.



 



Third, the dwell at the higher temperature is more important because of the much higher creep rates and therefore a more complete creep process. Thus, in an asymmetric cycle, the inputed dwell should not be just an average of the high and low-T dwells, but needs to be judged according to the T's involved. There have even been arguments advanced by some that because of the slow creep rates at the lower T, it can be ignored altogether. [Not that I agree with this argument]



 



            For the example with 6 minute power-on (assume system reaches thermal equilibrium after 1 minute) followed by 54 minute power off, the proposed tD = 6 minutes and proposed Tsj = 10% T(high) + 90%T(low). So if T(high) = 70C and T(low) = 50C, then average Tsj = 10% (70C) + 90% (50C) = 52C. Is there a better way to make a first order approximation for the values tD and Tsj for fatigue analysis?  Is there a way to quantify the error with this approach compared to a symmetrical duty cycle? 





Fourth, your 6/54 minute argument would give you somewhat of an overprediction of the actual cycles, because the hysteresis loop will be larger because of the 54-minute dwell at T(low)--the actuals involved would determine the level of inaccuracy.



 



            For the purposes of discussing analysis methods and accuracy, let’s define a “hot case” where the maximum T(high) could be as high as 85C with the T(low) at 50C. Similarly, there will be a “cold case”, which is just an offset from the hot case. In the cold case, let’s say the T(high) could be as high as 0C with the T(low) at -35C. What is the expected level of “inaccuracy” for the “hot case” and the “cold case” assuming the same 10% duty cycle applies in either case? 





Fifth, it is these kind of judegements by which we consultants earn our keep.



 



            Thank you for both your charitable and paid support.



Werner



 



-----Original Message-----

From: Nieznanski, John A - SSD <[log in to unmask]>

To: [log in to unmask]

Sent: Mon, 30 Mar 2009 4:05 pm

Subject: [TN] solder fatigue predictions for highly asymmetrical duty cycles



Hello Tech-Net Gurus,









The solder fatigue parameters called out in IPC-D-279, IPC-SM-785 and IPC-9701 all assume symmetrical (i.e. 50%) duty cycles and temperature swings. This raises the question as to how far these calculations can be pushed to predict solder fatigue in low duty cycle, variable duty cycle or high duty cycle applications.









In particular, Tsj ( = mean cyclic solder joint temperature), and tD ( = half-cycle dwell time in minutes) are both used and are directly affected by duty cycle. It is simple enough to recalculate these values based on asymmetrical duty cycles, but how do we know that the predicted solder fatigue results are still valid? If we know, do we know what assumptions are required to 

make the results valid? This seems like a fairly common situation. Has anyone correlated measured results to predictions in this regard?









Specifically, there are numerous caveats in the specs including for example, high-frequency (e.g, vibration) conditions where tD < 1 second, but none of these caveats apply here.









For example, with a power on dwell time of 6 minutes (system reaches thermal equilibrium in < 1 minute) and a power off dwell time of 54 minutes (10% duty cycle), I assume I can simply use tD = 6 minute dwells and Tsj = average solder joint temperature over 60 minute cycle. Do you agree with this approach?









Another potential case of interest is if the duty cycle is reduced to something less than 1 minute (but more than 1 second; not a vibration situation), such that the stabilized operating temperature is not reached. Can any valid fatigue calculations be performed in these cases if I can determine a valid Tsj for a 1 minute tD?









Thanks in advance for your insights and assistance.









Best regards,









John N.



















 

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