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Subject:
From:
Hernefjord Ingemar <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Hernefjord Ingemar <[log in to unmask]>
Date:
Tue, 31 Mar 2009 09:38:07 +0200
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 ...the tricky part is getting all the necessary info, AND getting correct info.

You see what I mean? Try to solve this equation: x+y=    
nothing after the equals-sign, not easy to do any calculation.

has nothing to do with age, rather lack of knowhow. That's why we need many werners..

Inge



-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Werner Engelmaier /*
Sent: tisdag 31 mars 2009 02:01
To: [log in to unmask]
Subject: {Spam?} Re: [TN] solder fatigue predictions for highly asymmetrical duty cycles

 Hi Inge,
You are going super-conservative in your old age. Heck, I have had accelerated tests with mean cyclic lives of 100 cycles and others with no failures in 100,000 cycle---It all depends.
If you understand the load drivers and the connections to cyclic life, you can execute a proper Design-for-Reliability in almost all cases; the tricky part is getting all the necessary info, AND getting correct info.

Werner


 


 

-----Original Message-----
From: Inge <[log in to unmask]>
To: [log in to unmask]
Sent: Mon, 30 Mar 2009 6:28 pm
Subject: Re: [TN] solder fatigue predictions for highly asymmetrical duty cycles









not an answer, but some reflections....?
?

I'm not a guru, more of a practical gnu. We have some math specialists who have produced models and calculations that make a normal reader exhausted to go from page 1 to page 200. After going through some reports like that, you feel rather disoriented. So, in order to know about the failure modes and six sigma, Time to Failure and such parameters, we decided to go the hands-on way. We 'simply' produced a lot of cloned boards with a substantial lot of components on, and started temp cycling with various symmetries and limits. Believe it or not, we have passed 10,000 cycles in some cases. The result will not be known until the end of this year. This method is not very comfortable either, making all these hundreds of microscope inspections and measure daisy chains and other stuff. Because our customer wants this way, we simply do it. Personally, I prefer neither of the ways, but more of a cautious and well performed design.  Follow the derating rules, don't buy components from unknown manufacturers,  hold back when the design engineers excess in very large or very odd boards,  keep to a board producer you know, don't mix extremly hot components with mW components and a lot more of goodies .  Sounds like stopping the development of new technology, but after reading Toyota's LEAN thinking, it seems as making many small development steps are safer, than to make a brand new super design. In earlier days, we had time to make prototypes, take our time and make a small pre-series, then introduce improvements, longlife test and slowly start series production. 
Now we go directly from CAD engineering to production....?

says an old dog?
?

Inge?
?


----- Original Message -----
From: "Nieznanski, John A - SSD" <[log in to unmask]>?

To: <[log in to unmask]>?

Sent: Monday, March 30, 2009 10:05 PM?

Subject: [TN] solder fatigue predictions for highly asymmetrical duty cycles?
?


Hello Tech-Net Gurus,?
?

The solder fatigue parameters called out in IPC-D-279, IPC-SM-785 and
IPC-9701 all assume symmetrical (i.e. 50%) duty cycles and temperature swings. This raises the question as to how far these calculations can be pushed to predict solder fatigue in low duty cycle, variable duty cycle or high duty cycle applications.?
?

In particular, Tsj ( = mean cyclic solder joint temperature), and tD ( = half-cycle dwell time in minutes) are both used and are directly affected by duty cycle. It is simple enough to recalculate these values based on asymmetrical duty cycles, but how do we know that the predicted solder fatigue results are still valid? If we know, do we know what assumptions are required to make the results valid? This seems like a fairly common situation. Has anyone correlated measured results to predictions in this regard??
?

Specifically, there are numerous caveats in the specs including for example, high-frequency (e.g, vibration) conditions where tD < 1 second, but none of these caveats apply here.?
?

For example, with a power on dwell time of 6 minutes (system reaches thermal equilibrium in < 1 minute) and a power off dwell time of 54 minutes (10% duty cycle), I assume I can simply use tD = 6 minute dwells and Tsj = average solder joint temperature over 60 minute cycle. Do you agree with this approach??
?

Another potential case of interest is if the duty cycle is reduced to something less than 1 minute (but more than 1 second; not a vibration situation), such that the stabilized operating temperature is not reached. 
Can any valid fatigue calculations be performed in these cases if I can determine a valid Tsj for a 1 minute tD??
?

Thanks in advance for your insights and assistance.?
?

Best regards,?
?

John N.?
?


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