I posted this on the PADS design listserver too.
I've run into customers like this also. In this case I made a special
library, used only with this customer, that had all the SMD parts with a
keepout placed under the component tied to layer "top".
I won't tell you what I named the layer.
And it sure does choke off a boatload of routing channels.
Then every time I got a board to do for them I increased the cost by 5%,
then 10%, then 15%, and the last one was 20%. I consider it an
aggravation factor.
They keep paying. <shrug>. Maybe 50% next time?
Wilson
pcbdznr at yahoo
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Thayer, Wayne
Sent: Wednesday, March 18, 2009 9:17 AM
To: [log in to unmask]
Subject: Re: [TN] Traces and vias under components
I have had customers like this too. These are the same guys who will
bring up the theory of "acid traps" and are so scared of "exposed
copper" (really just areas which aren't covered with mask which you
don't intend to solder to) that they won't use it even if it improves
yield. All of these are part of "good design folklore".
True, if metal under components can be avoided at no cost then that is
preferable for rework/board mod/test issues. But the improvement is
extremely marginal unless the board is poorly designed and manufactured.
If a solder bridge does happen in an area which is not visually
inspectable, then it is more expensive to diagnose. But first we have
to have bad mask design and/or placement, and then we have to have stray
solder get under the part.
These same customers go berserk when you suggest using a single wire
jumper to eliminate two layers of board and blind vias. "How dare you
start implementing 'white wires' before the first run is even made to
work!".
Customer is "KING". We make like they tell us. It is our job as
designers to tell them the consequences of what we perceive as
micro-management (as long as we don't tick them off when we tell them!).
Wayne Thayer
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Upton, Shawn
Sent: Wednesday, March 18, 2009 11:59 AM
To: [log in to unmask]
Subject: Re: [TN] Traces and vias under components
Rework issues? Hard to cut a trace under a component. Also, are they
using tented vias? Untented via's are easy to probe, while tented ones
are bit harder.
Shawn Upton, KB1CKT
Test Engineer
Allegro MicroSystems, Inc
[log in to unmask]
603.626.2429/fax: 603.641.5336
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Kevin Glidden
Sent: Wednesday, March 18, 2009 11:54 AM
To: [log in to unmask]
Subject: Re: [TN] Traces and vias under components
If it's a space issue, that's your argument.....if not, why argue?
Customer is always right........
-----Original Message-----
From: wheels [mailto:[log in to unmask]]
Sent: Wednesday, March 18, 2009 11:01 AM
To: [log in to unmask]
Subject: [TN] Traces and vias under components
Guys,
We have a customer which we are designing a mostly SMT board for that
requires all traces and vias not to be under components. This would also
include any planes being under the components. I guess in the past they
had a board designed by some else that had a shorting problem with
traced and vias under the components. They are insistence that this is
the way it has to be. Has anyone else had experience with this sort of
demands? This is not for space, military, high voltage, high vibration
or a medical application.
Can anyone think of anything we could tell they to change their mind?
Thank you,
wheels
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