I read this thread with great interest and sorry if my comments spoil the
serious discussion here. It all comes down to the basic question, Why 6
sigma, why Cpk, does it really matter? (I only discuss in-process parameters
here)
One can easily tell from the original post that how easy Cpk value can be
manipulated by just open up the spec limits. It goes from 1.33 (+/- 25%) to
1.66 (+/-50%) by doing nothing to the process itself. So is Cpk of 1.66
really better than 1.33? Only when you present it to the customer.
Unfortunately since all the customers care about are certain value of Cpk so
it somehow becomes a common practice to just cheat on the specs. This
practice will backfire because now you don't react to the true spec limits.
(Yes, some people use the old narrower spec limits as control limits, it is
wrong and just another way of cheating)
For in-process parameters, does 6-sigma really matter? For a Cpk of 1.66
(5-sigma), it means 233 out of 1 million data point are out of spec (but not
necessary creating defects on final products). Depending on what you are
monitoring, that could be an over-achievement for most in-process parameters
(and costly).
Back to the original question. To make the customer happy, stay at +/-50%.
To really make sure your process are the way you want it to be, keep it at
+/-25% so you can quickly react to real-time problem. To truly use control
charts for long term process control, it doesn't matter because out of
control situations have nothing to do with spec limits.
All of the above are under the assumption that the data are normal
distribution and process is stable, otherwise SPC, Cpk have no meaning.
Regards,
Jason Zhao
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Andy Ng
Sent: Tuesday, December 02, 2008 1:07 PM
To: [log in to unmask]
Subject: Re: [TN] What are the industrial standards for Solder paste
printing limits?
Hi Rudolph,
Yes that's what I'm trying to say. A Cpk of 1.66 is actually 5 sigma,
which if measured for Cp is actually 10 std deviations, since you're
measuring for both LSL and USL. If your customer wants to have a
6-sigma, for a Cp calculation it will need to measure across 12 std
deviations. For Cpk, you need to find the minimum of either the lower
or the upper limits, in the solder paste printing height, will be the
upper.
As Richard mentioned, applying a kapton tape to mask off no-loads
would add to the thickness. There are also other factors, such as if
your foil is filmsy, ie. not fully stretched, or if you're using a
carrier for your PCB, or even if the stencil height is not properly
adjusted, ie. too close to the PCB, causing the stencil to "bow",
hence a larger gap in the center of the PCB than the edges.
In all cases, the paste deposit will be thicker than the thickness of
the foil. However, an average of additional 1 mil might be too large.
Our vendor has an average of about 5.5 - 5.6 mils for a 5-mil foil to
account for these factors. This is probably why it is hard to get the
Cpk to 1.66, since your mean is not exactly the midpoint of your USL
and LSL, which is 5 mils. The constant "K" is calculated to offset the
difference between your midpoint (5 mils) and your mean (6 mils) to
derive to a lower Cpk.
Hope this helps.
Andy
Quoting Rudolph yu <[log in to unmask]>:
> Andy:
>
> Check out the website. Actually Cpk 1.66 = 5 sigma, cpk 1.33 is = 4
> sigma. One will need a cpk of 2 in order to get to the 6 sigma
> region.
> The averge is about .15mm which is around 6 mil. This is another
> thing that our process engineer cannot answer me directly why the
> solder paste dispoisition is 1 mil more than the the stencil
> thickness on average? Any help?
>
> http://www.isixsigma.com/library/content/sigma_cpk_conversion_table.asp
>
> I dont know what the sample size the software is using. I am still
> waiting for the answer from the SPI manufactuer.
>
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