Kapton tape is 1 mil thick. If it is used to mask off no-loads on the
stencil, that can be a reason.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Rudolph yu
Sent: Tuesday, December 02, 2008 12:41 AM
To: [log in to unmask]
Subject: Re: [TN] What are the industrial standards for Solder paste
printing limits?
Andy:
Check out the website. Actually Cpk 1.66 = 5 sigma, cpk 1.33 is = 4
sigma. One will need a cpk of 2 in order to get to the 6 sigma region.
The averge is about .15mm which is around 6 mil. This is another thing
that our process engineer cannot answer me directly why the solder paste
dispoisition is 1 mil more than the the stencil thickness on average?
Any help?
http://www.isixsigma.com/library/content/sigma_cpk_conversion_table.asp
I dont know what the sample size the software is using. I am still
waiting for the answer from the SPI manufactuer.
> Date: Mon, 1 Dec 2008 16:29:30 -0800> From: [log in to unmask]> Subject:
> Re: [TN] What are the industrial standards for Solder paste printing
> limits?> To: [log in to unmask]> > Hi Rudolph,> > If I'm not mistaken, a
> 1.66 Cp means you're satisfying across 10 std > deviations, not 6.
> Measuring across 6 std deviations would yield a Cp > of 1.0. However
> even with inclusion of outliers, especially for > printing a high
> volume batch, reaching a 1.66 using a 25% tol would be > achievable.
> What is your std deviation and sample size?> > Regards,> Andy> > >
> Quoting Rudolph yu <[log in to unmask]>:> > > Hi Andy:> >> > In
> theory, I think the Panasonic SP18 should be able to achieve 1.66 > >
> cpk. But the data that we collected is not pointing to that..> > One
> reason I think is due to the outliners that we are having > >
> difficulties to remove from the calculation. (using the software > >
> that comes with the SPI machine)> >> > I was just reading couple
> papers on the internet, and people are > > using +/-50% USL/LSL for
> their experiments. I just wish I could find > > some literature that
> says 50% is the industrial standards. If I > > feel more comfortable
> to set the process control limits at +/- 25%.> >> > Rudolph> >> >> >>
> >> >> >> >> >> Date: Mon, 1 Dec 2008 15:17:20 -0800> From:
> [log in to unmask]> > >> Subject: Re: [TN] What are the industrial
> standards for Solder > >> paste printing limits?> To: [log in to unmask]>
> > Hi Rudolph,> > > >> What's your mean and std dev? With 5 mils
> thickness for 50% > >> tolerance, > the USL would be 7.5 mils and LSL
> is 2.5 mils. This > >> tolerance is a bit > too high. I think 25% is a
> more reasonable > >> tolerance, unless there are > no-loads that
> you're taping with tape > >> on the stencil. This will create > a
> larger gap, and thus much > >> thicker deposits. Even with 25%, you >
> should be able to get > >> process cap index of 1.66 across 6 std
> deviations.> > Andy> > > >> > >> > -----Original Message-----> > From:
> TechNet > >> [mailto:[log in to unmask]] On Behalf Of Rudolph yu> > Sent:
> Monday, > >> December 01, 2008 3:52 PM> > To: [log in to unmask]> >
> Subject: [TN] > >> What are the industrial standards for Solder paste
> printing> > > >> limits?> >> > Hi Technetees:> >> > One of our
> customers had asked > >> us to show that our solder paste
> despoisition> > process is capable > >> to acheive Cpk at 1.66 (6
> sigma). We just built a> > thousands of > >> pilot boards, and the SPC
> report I got from the TRI's SPI> > > >> machine indicated that the
> process is able to reach that > >> goal.......however> > the software
> sets the upper limit and lower > >> limits for height, area and> >
> volumn to about +/-50%. Is this > >> reasonable to have such a high
> variance in> > the printing process? > >> (We use 5 mil stencil with
> 0201 and fine picthc> > aperature). If > >> I change the limits to +/-
> 25%, the Cpk will become around> > 1.33 > >> ( 4 sigma)...should I
> claims that we can acheive 1.66, and point > >> out> > that the wide
> tolerence was set by the machine expert, or > >> should I limit> > the
> tolerance spread, and hope that customer > >> will accept lower Cpk.>
> >> >> > I guess my quesiton is " Is +/- > >> 50% tolerance a resonable
> limits for paste> > printing process?"> > >> >> >> >> > BTW the AOI
> and AXI yield is in the high 98 and low 99 > >> range for this> >
> design.> >> > Thanks> > Rudolph> >> >> > > >>
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