TECHNET Archives

November 2008

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
Hernefjord Ingemar <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Hernefjord Ingemar <[log in to unmask]>
Date:
Tue, 25 Nov 2008 15:37:03 +0100
Content-Type:
text/plain
Parts/Attachments:
text/plain (112 lines)
noone said anything about what kind of dielectric and nor what thickness. On the other hand, at 600 MHz the losses may not be significant. S/N seems to be more important. And signal integrity. Interesting to follow your debate, these matters are not online very often.
Inge

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Upton, Shawn
Sent: den 25 november 2008 15:02
To: [log in to unmask]
Subject: Re: [TN] Stripline Traces and Plane Splits

I'd prefer (if it were my design) for complete copper pours, unless if I knew that there were not any cross-currents.  Also, I was not giving a complete stackup, but rather just a few layers--while there is a bit symetry with putting diff pars on either end of the stackup, I think one would save on a groundplane by "stacking" them next to each other.

Plus, if this is high speed, one has to worry about the via's.  At some point, they become stubs.  I have no experience, but something tells me that it'd be better to put these route layers on the other side of the board, that way, the signal travels most of the via path, preventing the via from being a stub.  Of course, then the via spacing and diameter comes into play--so then blind via's come into the picture.  At which point I'd rather put all digital on one side of the board, analog on the other, with blind via's going from say L1 down to L5 or L6 (depending upon how the board gets made).

At 600MHz, hmm, not sure but since it's squarewave signals then rise/fall time will determine if you'll get degredation from the stubs.
Probably not that big of an issue, but something to think about, if this is a thick board.

I see Dave's recent response, that does make it harder, as I suspect it's analog and digital, both sides of the board.  I'd think about doing a parts placement, and then route just the diff pairs.  Maybe you could get away with just one layer of diff routing?  That may free up some layers for solid plane usage, and/or reduce layer count.  This will then impact diff pair widths.  But more importantly, it could impact board
performance: if all the layers are equi-distant, then the coupling capacitance goes down, and then the board no longer act quite as a capacitor as before.  If you do reduce layer count, you may want to spec some of the critical high speed (well, high di/dt) power planes to be closer to one another, in order to make a better capacitor out of it.

Shawn Upton, KB1CKT
Test Engineer
Allegro MicroSystems, Inc
[log in to unmask]
603.626.2429/fax: 603.641.5336

-----Original Message-----
From: Hernefjord Ingemar [mailto:[log in to unmask]]
Sent: Tuesday, November 25, 2008 8:49 AM
To: TechNet E-Mail Forum; Upton, Shawn
Subject: RE: [TN] Stripline Traces and Plane Splits

What a nice symmetry! 
But I wonder what became of AGND? And are the ground planes complete copper planes (no split)?
Inge

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Upton, Shawn
Sent: den 25 november 2008 14:15
To: [log in to unmask]
Subject: Re: [TN] Stripline Traces and Plane Splits

For some reason, I'm looking at this and wondering, "why so many planes"?  It's one thing if there is a lot of connections, as the planes do make connections easy.  [Ie, just drop a via to get to GND or power.] But since these planes are all capacitively coupled together anyhow (big parallel plate capacitor), I have to wonder if it's really optimal.
Just an observation, it could be just for easier route/redesign--unfortunately, I've never taken a class on high speed mixed mode design--I just look at the return currents, and go from there.

This looks like a mixed mode design, possibly with parts on both sides of the board.  Since AGND is buried in the stackup, I'll assume that the analog signals are slow speed, and possibly not small signal either.
Otherwise, AGND would not be buried, but rather near analog routing areas.

I'm not sure what the split DGND planes are for; are they split into areas on the board to prevent crosstalk, or for different logic voltage families, or __?  In the case of L3 differential routing, if a signal pair never crosses the split, you should be ok.  However, when said diff pair goes up to L1 (or down to L14), you should pin the DGND's together
(via's) to provide return current paths *for both planes*, both of which will have return currents.  If you can, keep said diff pairs from crossing any split, and pin either end of said pairs DGND's together.

As for L12 diff pairs, you might be ok, but it really depends upon the signal speed, and the location of said decoupling capacitors--which, in this case, are going to couple the ground return currents.  Basically, in the area where the signal enters L12 should have DVCC coupled to DGND via high quality capacitors (most likely the case, as they would be used for VCC anyhow--but get some close to the transmitter pins too).  The reciever ends should have the same caps.  And the signal again should not cross any splits.

I'd think about reversing L10 and L11, to get a DGND closer to L12.  It depends upon again the routing of those planes, and what L9 is carrying vs what L11 is.  Actually, I'd argue for changing the stackup, and perhaps getting something along the lines of "DVCC, DGND, diff pair, DGND, diff pair, DGND, DVCC".

Shawn Upton, KB1CKT
Test Engineer
Allegro MicroSystems, Inc
[log in to unmask]
603.626.2429/fax: 603.641.5336

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of David Baldwin
Sent: Monday, November 24, 2008 4:40 PM
To: [log in to unmask]
Subject: Re: [TN] Stripline Traces and Plane Splits

Shawn:

It's a 14 Layer board as it has a lot of critical voltages that need to be planes.  If I had a plane for each voltage, I'd need a 24 layer board!  I'm only using the surface layers and L3 & L12 for routing.

1 - Primary
2 - DGND
3 - Trace
4 - Split DGND
5 - Split DVCC
6 - Split AVCC
7 - AGND
8 - Split AVCC
9 - DVCC
10 - DGND
11 - Split DVCC
12 - Trace
13 - DGND
14 - Secondary

I'm not sure what the signal speeds are, I'll need to check with the engineer.  I worked with an engineer in the past who said that it's not real detrimental when you have a solid plane on one of the sides.  It's not ideal or desirable, but you still will achieve acceptable results.
This was based upon his real world results.

Thanks,

Dave

---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 15.0 To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or
(re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the
posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
-----------------------------------------------------

---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 15.0 To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
-----------------------------------------------------

---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 15.0
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
-----------------------------------------------------

ATOM RSS1 RSS2