What a nice symmetry!
But I wonder what became of AGND? And are the ground planes complete copper planes (no split)?
Inge
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Upton, Shawn
Sent: den 25 november 2008 14:15
To: [log in to unmask]
Subject: Re: [TN] Stripline Traces and Plane Splits
For some reason, I'm looking at this and wondering, "why so many planes"? It's one thing if there is a lot of connections, as the planes do make connections easy. [Ie, just drop a via to get to GND or power.] But since these planes are all capacitively coupled together anyhow (big parallel plate capacitor), I have to wonder if it's really optimal.
Just an observation, it could be just for easier route/redesign--unfortunately, I've never taken a class on high speed mixed mode design--I just look at the return currents, and go from there.
This looks like a mixed mode design, possibly with parts on both sides of the board. Since AGND is buried in the stackup, I'll assume that the analog signals are slow speed, and possibly not small signal either.
Otherwise, AGND would not be buried, but rather near analog routing areas.
I'm not sure what the split DGND planes are for; are they split into areas on the board to prevent crosstalk, or for different logic voltage families, or __? In the case of L3 differential routing, if a signal pair never crosses the split, you should be ok. However, when said diff pair goes up to L1 (or down to L14), you should pin the DGND's together
(via's) to provide return current paths *for both planes*, both of which will have return currents. If you can, keep said diff pairs from crossing any split, and pin either end of said pairs DGND's together.
As for L12 diff pairs, you might be ok, but it really depends upon the signal speed, and the location of said decoupling capacitors--which, in this case, are going to couple the ground return currents. Basically, in the area where the signal enters L12 should have DVCC coupled to DGND via high quality capacitors (most likely the case, as they would be used for VCC anyhow--but get some close to the transmitter pins too). The reciever ends should have the same caps. And the signal again should not cross any splits.
I'd think about reversing L10 and L11, to get a DGND closer to L12. It depends upon again the routing of those planes, and what L9 is carrying vs what L11 is. Actually, I'd argue for changing the stackup, and perhaps getting something along the lines of "DVCC, DGND, diff pair, DGND, diff pair, DGND, DVCC".
Shawn Upton, KB1CKT
Test Engineer
Allegro MicroSystems, Inc
[log in to unmask]
603.626.2429/fax: 603.641.5336
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of David Baldwin
Sent: Monday, November 24, 2008 4:40 PM
To: [log in to unmask]
Subject: Re: [TN] Stripline Traces and Plane Splits
Shawn:
It's a 14 Layer board as it has a lot of critical voltages that need to be planes. If I had a plane for each voltage, I'd need a 24 layer board! I'm only using the surface layers and L3 & L12 for routing.
1 - Primary
2 - DGND
3 - Trace
4 - Split DGND
5 - Split DVCC
6 - Split AVCC
7 - AGND
8 - Split AVCC
9 - DVCC
10 - DGND
11 - Split DVCC
12 - Trace
13 - DGND
14 - Secondary
I'm not sure what the signal speeds are, I'll need to check with the engineer. I worked with an engineer in the past who said that it's not real detrimental when you have a solid plane on one of the sides. It's not ideal or desirable, but you still will achieve acceptable results.
This was based upon his real world results.
Thanks,
Dave
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