Hi John,
I cannot talk to the JEDEC criterion--it simply may be a simplification of the criterion given in IPC-SM-785.
That criterion comes from the extensive work at Bell Laboratories and the IEEE Compliant Lead Task Force in the first half of the 1980's.
The whole point of the failure criterion is to detect electrically a solder joint failure as soon as possible after full mechanical fracture has occurred. Since SJs are loaded in shear, the fracture surfaces do not separate,and it also needs to be remembered, that the first SJ that fails is surrounded at least on 2 sides by SJs that have not as yet failed.
The 1000 ohms comes from the capability of the Event Detectors at that time--they can do much better than that nowadays.
The additional 9 failure indications with 1.1x Nf come from the need to exclude false failure indicatons coming from electrically noisy environments; however, with this confirmation it is the first failure indication that counts. We do know however also, that actual failure [in the mechanical sense] actually occurred somewhat earlier. This failure indication provides one data point on a Weibull graph--aditional channels/daisy-chains provide additional data points as they fail.

Q1--This does not "allow a small number of infrequent events to occur before counting tham as failures." The premise to this Q1 is false.

Q2--This is not a statistical argument--to provide statistical robustness a minimum sample size of 32 is prescribed. Nor is it application dependent. It is dependent on the physics-of-failure of the design details and loading conditions.You should be taking my workshop on SJ reliability fundamentals at the upcoming IPC EXPO/APEX in Las Vegas.

Q3--No, these criteria are there to detect as efficiently as possible SJ failures--they have nothing to do with what is happening at a given application.

?Werner


 


 

-----Original Message-----
From: Nieznanski, John A - SSD <[log in to unmask]>
To: [log in to unmask]
Sent: Tue, 18 Nov 2008 9:48 pm
Subject: [TN] Origin and Application of Various Failure Criteria Standards










Hi List Gurus,

I have a few questions on these standards that I could not answer on my own 
after some research. If there are links or archives that cover these topics, I 
will be happy to pursue this off list. To refresh our memories:

- The IPC-SM-785 (1992) and IPC-9701A (2006) failure criteria is met anytime 
there are 10 failures (~1 microsecond events) on any channel with all of the 
failures occurring within a number of cycles that is 10 percent (10%) of the 
cycle number at the first failure on that channel.

- The JESD 22-B111 failure criteria is met anytime there are 3 failures (~1 
microsecond events) on any channel with all of the failures occurring within 5 
cycles after the first failure on that channel.

- The JEDEC standard is application specific "Board Level Drop Test Method of 
Components for Handheld Electronic Products" while the IPC standard is only 
specific to SMT devices, regardless of application.

- In both cases, the standards call out 1000 ohm thresholds are to be used based 
on possible sensitivity to false failures from electrical noise when loop 
resistance thresholds are set lower than 1000 ohms.

Q1. What is the basis for allowing 10 events within 10% of first event (for IPC) 
and 3 failures within 5 cycles (for JEDEC)? This allows small numbers of 
infrequent events to occur before counting them as failures. This may provide a 
false sense of security, quality and reliability to the end user that may not 
always be justified.

Q2. Is this a statistical argument (a "few" events occurring in a relatively 
"small" sampling window are likely to be correlated, not random or noise 
generated), an application dependent argument, both or neither?

Q3. Is it common to tailor these criteria for the application and/or customer at 
hand? For example, it seems that a low impedance analog circuit or 100 ohm 
differential signaling application may be more sensitive to interconnect events 
below 1000 ohms than a traditional single ended digital switching circuit with 
megohms of input impedance.

Thank you for your time.

Regards,
John Nieznanski


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