This table seems very valuable.
Pete , can You add additional information?
Which board thicknesses are investigated?
Which finishes are investigated?
I attach the information of the SMTA-Paper, reporting some investigations on OSP-finish :
IMPROVING HOLE-FILL IN LEAD-FREE SOLDERING OF THICK PRINTED CIRCUIT BOARDS WITH OSP FINISH
Sanmina-SCI Corporation (LF2)
from SMTA Conference 2008, Orlando, Florida, August 17 -21, 2008
They told that they had a big rejection rate with OSP finish, where gap is less than 11,5 mils. This leads to different values to Your table?.
Sincerly
Michael Jeremias
Industrial Engineering (OPPI41)
Electronics Production
((( Defence Electronics
EADS Deutschland GmbH
89077 Ulm
Tel.: +49 (0) 7 31.3 92-5533
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-----Ursprüngliche Nachricht-----
Von: TechNet [mailto:[log in to unmask]] Im Auftrag von Pete Houwen
Gesendet: Mittwoch, 29. Oktober 2008 14:07
An: [log in to unmask]
Betreff: Re: [TN] How to improve solder filling and wetting contact angles for thermal vias at wave soldering process.
We did some testing of design parameters when we switched to lead-free, and found that the lead-hole ratio is more critical. We also found that top side pad size is irrelevant for hole fill, but large bottom side pads can adversly affect hole fill. Using this chart, we are able to achieve 75% with regularity (and we do not have the best process controls in our plant):
Lead Range Pad Size Hole Size
.000-.017 0.05 0.026
.018-.022 0.06 0.035
.023-.027 0.07 0.04
.028-.032 0.07 0.046
.033-.042 0.08 0.052
.043-.052 0.09 0.062
.053-.063 0.1 0.073
.064-.076 0.11 0.086
.077-.086 0.12 0.096
.087-.106 0.14 0.116
.107-.115 0.15 0.125
(dimensions in inches)
standard plane connects are thermal relief, using (4) .008" spokes.
This testing was done only to establish design parameters, there are plenty of process parameters that will affect hole fill. But if your design parameters aren't good, all the process tweaks in the world won't fix trhe problem.
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