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October 2008

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Subject:
From:
Dwight Mattix <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Dwight Mattix <[log in to unmask]>
Date:
Thu, 16 Oct 2008 09:01:17 -0700
Content-Type:
text/plain
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text/plain (102 lines)
When we've specified heavy copper vias in the past it required button 
plating and planarization to maintain a workable total outerlayer Cu 
thickness.

In the words of our supplier "it's complicated, but at least it's expensive."

At 08:26 AM 10/16/2008, Dennis Fritz wrote:
>Surprised no one has mentioned the plating of surface features at 
>the same time as plating copper in?the holes (plating shut).? There 
>will be some pad around the lip of the hole, and this will plate 
>very thick - what is the diameter of the via holes?.? Say they are 
>10 mils, to plate them shut, you will have about 5 mil high surface 
>features at the surface pads.? That is assuming a good copper bath 
>that plates 1:1 in the hole and on the surface.? Then, your fab shop 
>will have to sand down the surface to remove most of the 5 mil high 
>"rims" around the holes.? And, you say components are above the vias 
>- you want very planar circuit traces under those, not 5 mil "lumps".?
>
>You are approaching the technology of "wrap" plating, which not all 
>shops can do routinely.?
>
>Denny Fritz
>MacDermid, Inc.
>
>
>-----Original Message-----
>From: Dave Connitt <[log in to unmask]>
>To: [log in to unmask]
>Sent: Thu, 16 Oct 2008 10:35 am
>Subject: Re: [TN] Problems with plating vias closed
>
>
>
>Hi Pete,
>This is a research/development project. The vias are currently tented,
>plus some are under a couple of 100 pin QFP's. I would have to move the
>vias out from under the FPGA's or risk solder balls once I untented
>them. Since this is a development project, I doubt they will spin the
>board again unless there is some other issue. We rarely wave solder
>boards anymore as there are very few thru hole parts on them anymore.
>The wave was a great way to fill vias with solder. Ah, the good old
>days..
>Dave Connitt CID+
>Printed Circuit Designer
>KDI Precision Products, Inc.
>A Wholly Owned Subsidiary of:
>L3 Communications
>3975 McMann Road
>Cincinnati, Ohio 45245
>Ph. 513- 943-2010   Fax 513-943-2288
>
>
>-----Original Message-----
>From: Pete Houwen [mailto:[log in to unmask]]
>Sent: Thursday, October 16, 2008 9:36 AM
>To: [log in to unmask]; Connitt, Dave @ KDI
>Subject: Re: Problems with plating vias closed
>
>Is this just a matter of closing the holes?  Rather than having your PCB
>supplier try to plate the holes full, can you let them (partially) fill
>during soldering?
>
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