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October 2008

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Subject:
From:
Dwight Mattix <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Dwight Mattix <[log in to unmask]>
Date:
Thu, 16 Oct 2008 08:39:11 -0700
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what's in the way of having them filled w/ non-conductive epoxy after 
via plating but prior to final surface finish?

dw

At 07:35 AM 10/16/2008, Dave Connitt wrote:
>Hi Pete,
>This is a research/development project. The vias are currently tented,
>plus some are under a couple of 100 pin QFP's. I would have to move the
>vias out from under the FPGA's or risk solder balls once I untented
>them. Since this is a development project, I doubt they will spin the
>board again unless there is some other issue. We rarely wave solder
>boards anymore as there are very few thru hole parts on them anymore.
>The wave was a great way to fill vias with solder. Ah, the good old
>days..
>Dave Connitt CID+
>Printed Circuit Designer
>KDI Precision Products, Inc.
>A Wholly Owned Subsidiary of:
>L3 Communications
>3975 McMann Road
>Cincinnati, Ohio 45245
>Ph. 513- 943-2010   Fax 513-943-2288
>
>
>-----Original Message-----
>From: Pete Houwen [mailto:[log in to unmask]]
>Sent: Thursday, October 16, 2008 9:36 AM
>To: [log in to unmask]; Connitt, Dave @ KDI
>Subject: Re: Problems with plating vias closed
>
>Is this just a matter of closing the holes?  Rather than having your PCB
>supplier try to plate the holes full, can you let them (partially) fill
>during soldering?
>
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