A product I am working on recently experienced a higher than normal drop out 
both internally and externally due to open traces. Microsection analysis of 
several of the failing PCBs found barrel cracks, plating folds, and insufficient 
wall thickness.

Our fabrication specification requires "Copper Plating, Annular Ring, Conductor 
Spacing, and Solder Mask requirements shall be in accordance with IPC-6012, 
Class 3". PCB is 6 layers or IPC Type 3.

I applied IPC-6012 tables 4-2 Sampling Plan and 4-3 Acceptance Testing and 
Frequency to give the following:

- Table 4-3 specifies sample frequencies of 2.5 for Plating / Coating Thickness 
and 0.1 for Hole Plating Thickness (structural integrity after stress), both per 
panel.

- Our lot size was approximately 2000 PCBs, yield is 6 PCBs from an 18" x 24" 
fabrication panel, therefore at least 330 fabrication panels would have been 
processed.

- From Table 4-2, my assumption is that lot size should be 330 panels, and 
the corresponding sample sizes for 0.1 is 125 and 2.5 is 16 (please correct me 
if I'm interpreting this incorrectly !).

Some questions: 

1. What governs how the fabricator applies the specification to their process. 
In other words, does a vendor have freedom to perform (in our case) 125 
samples / 16 samples from a single fabrication panel and then pass the other 
329 based upon those results, or is there some other specification which 
which the vendor must follow for sample identification ?
2. If so, how do I properly convey this to the vendor ?

We have since determined the cause was 1 of 7 sub lots at our vendor was 
improperly processed through desmear. It's my feeling that our Class 3 
requirement should have caught the failures at the fabricator if proper 
sampling / testing was performed - comments ?

Thanks,
Dave

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