1) Is it possible to cause inner layer shifting on only signal layers during
the assembly operations or will this be seen in the PCB fabrication testing?

Inner layer shift occurs or is the result of improper film punch, layer
punch, this would present itself as shift during the imaging process. Layer
shift (core layers) may also occur during lamination as a result of poor
pinning, excessive epoxy (as resin in prepreg), bad or no vacuum (especially
on high layer counts).

2) Can inner layers that create opens or shorts be latent or would the
effect be seen immediately? 

Yes, and yes. Depending upon the features the shift may cause direct shorts
or possibly opens (although rare). The latency would be caused by adjacent
features and contamination possibly bridging (do a search on dendritic
growth).

3) Would inner layers that do shift all shift the same way? In other words
would I get the same opens/shorts? What would be the proportion of possible
affected if not all? 

The shift would most likely present itself in a skewed manner although X and
Y registration issues are not totally uncommon. Doubtful you would see
proportional effects unless the board were perfectly symmetrical, and if
that were the case you would be building samples and not actual, usable
product.

4) Would the PCB stresses caused by lamination not be released prior to the
PCB test or is there enough residual stress still in the PCB at time of
assembly to cause an issue? 

Depends on what stresses you are referring to. If you are referring to
stress in the Z-axis, the board most likely will expand/contract a few more
times during additional processing including assembly. There should be
relatively little expansion in the X-Y axis, there will be some, but the
Z-axis expansion will tear the board apart before the X-Y axis expansion.

5) How would you know if you have inner layer shifting? 

I would know by inspecting layers either at AOI or visual, this is also
observed during drill (x-ray analysis), then again at post-etch inspection
(prior to solder mask application) but depending upon where the ground
planes are you may only observe down 1 or 2 layers into a multilayer. It
might present itself at electrical testing (see above) and then finally
during microsection evaluation.
 
I was just reading about etch back and some the test data related with the
process, is this part of the driver to develop this process? 

I don't understand your question above.

Franklin

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