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July 2008

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Subject:
From:
Ryan Grant <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, [log in to unmask]
Date:
Tue, 1 Jul 2008 10:14:31 -0600
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Hi Grunde,
 
You are correct, I totally missed the last statement of 3.5.3 where the
13mm maximum allowed defective length is indicated. It seems this means
the trace width can never measure narrower than the Gerbers, except in
isolated areas where there is a defect.
 
I don't consider that reasonable for traces; as you already said, it
doesn't allow for manufacturing tolerances. Based on the Certificate of
Compliance documents I get, I think I would have a tough time getting
boards if I held suppliers to that interpretation. Probably not a
problem when trace spacing is wide, but it does invite the board shop to
shift nominal trace width so that it is wider than designed, which
causes impedance values to run low.
 
I also agree with your min tolerance on large copper features and
specify similar numbers.
 
Thanks,
Ryan

________________________________

From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Tuesday, July 01, 2008 12:11 AM
To: TechNet E-Mail Forum; rgrant
Subject: Re: [TN] IPC-6012A - allowable conductor width reduction
interpretation?



Hi

IPC does not allow for a 20% reduction of the copper features, 13mm or
10% of a track can deviate up to 20% for class 2 and 3.
I don't think this is well formulated as it doesen't really allow for
manufacturing tolerances, I believe most manufacturers interpret this in
a more liberal manner and considers 20% as the manufacturing tolerance.
However, to let the 20% be valid for the larger copper features is a bit
thick in my opinion. I interpret the maximum allowed reduction on pads
as the absolute reduction on conductors. Meaning that if the board has
0,1mm tracks the maximum allowable reduction on pads is 0,02mm.

Best regards
Grunde




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Ryan Grant <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>

30.06.2008 21:43
Please respond to
TechNet E-Mail Forum <[log in to unmask]>; Please respond to
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To
[log in to unmask]
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Subject
Re: [TN] IPC-6012A - allowable conductor width reduction interpretation?






Hi Joe,

I interpret it the same and end up specifying specific BGA pad size
tolerances instead of using 6012.

By the way, per IPC, the conductor width should be measured from the
bottom of the pad, i.e. the interface between the copper and dielectric.
There is typically a 25um difference in width between top surface and
bottom surface, so measurements of pad width that only measure the top
surface might seem smaller than allowed.

Thanks,
Ryan

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Joe Macko
Sent: Monday, June 30, 2008 10:45 AM
To: [log in to unmask]
Subject: [TN] IPC-6012A - allowable conductor width reduction
interpretation?

All,



IPC-6012A with amendment 1, section 3.5.1, Conductor Width and Thickness
states, "When not specified on the master drawing the minimum conductor
width shall be 80% of the conductor pattern supplied in the procurement
documentation". The PCB suppliers interpret this to mean that BGA pads
for example can be 80% of the pad diameter specified in the procurement
documentation, which is the GERBER files unless specified otherwise and
still be acceptable per IPC-6012.



I am interested to hear how other users handle allowable reductions in
BGA pad size from that specified in the procurement documentation.
thanks



Best Regards,

-joe




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