The ageing effect of some dielectrics is large. It is quoted as percent

per LDR. Figures can be as high as 7% per LDR. (-7% hour 1, -7% next 10

hours etc) Reset is achieved by high temperature (Curie Point?) such as

soldering. So I've seen ICT fails for being too high when tested quickly

after reflow.

Close reading of some chip capacitor specs leads one to believe that

-100% plus infinity on tolerance is a valid spec.

I would look carefully at the spec of the capacitor designed in and

discuss with the board designer what is needed. It is quite possible

that the designer is unaware of the lack of stability in some

dielectrics.

Rex





Rex Waygood

Technical Manager

 

PartnerTech Poole Ltd 

Benson Road

Poole

Dorset BH17 0RY

United Kingdom

 

Tel: +44 (0)1202 674333

Fax: +44 (0)1202 678028

DDI: +44 (0)1202 338222

Mob: +44 (0)7887 997403

 

[log in to unmask]

www.PartnerTech.co.uk



-----Original Message-----

From: TechNet [mailto:[log in to unmask]] On Behalf Of Ioan Tempea

Sent: 01 July 2008 16:18

To: [log in to unmask]

Subject: Re: [TN] Ceramic Cap Value



Hi Ken,



We've seen this phenomenon twice in the past 4 months, high rate of ICT

failure on ceramic caps and had the same issue, replacing the parts

sometimes worked and sometimes didn't. We even have a painful open case

on this matter.



I need more clarifications from the group regarding this issue and how

to get around it.



The paper on aging asks to take the phenomenon into account when

designing the circuitry.

Does this mean the high failure rate Ken and I witnessed is borderline

design?



Can it be marginal testing method also?



Can it be anything else that design or testing?



Thanks,



Ioan







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