The washing process sloshes dirt all over the board and if the process is
really good, the dirt goes down the drain.
The smaller the spaces under the components, the harder it is to remove the
dirt there and the easier it is for the dirt to collect there.
If you are dealing with high voltages do not rely on the solder mask for
insulation; therefore no runs under components.
Solutions: make sure you have a very good and well controlled washing
process.
If you have high voltages across short distances you have high fields and
that is where the dirt collects and where the dendrites will grow.    
If the high voltage is across an SMT resistor, you can mitigate the problem
by placing two resistors in series. For caps, use a bigger body part.

Have fun,
Ahne 

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Phil Nutting
Sent: Wednesday, 04 June, 2008 09:34
To: [log in to unmask]
Subject: [TN] Removing soldermask under SMT devices

As we do more SMT boards with high power or high voltage we have seen some
failures we suspect are due to flux and other undesirable junk under some
SMT devices.  In researching cleaning processes (and failures) I have seen
some articles that show "our fault mode".  One solution seen in this
research suggests removing solder mask under SMT components to give a larger
space under the parts to allow the junk to be more easily removed during the
cleaning process.

Is this an industry problem and is removing the silkscreen under the devices
an industry solution?  If removing the silkscreen is what folks are doing,
what are the decision criteria being used as to which components get this
treatment?  Is it every component or just those that have the highest
likelihood of failure due to the current through or voltage across the part?

Thanks in advance.

Phil Nutting

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