Phil, what kind of voltages are you seeing problems with?  we design 
inverters for LCD backlighting and are familiar with voltages up to about 
3500vAC.  We dont remove ANY mask under components.  Our typical failure is 
often related to HV spacing requirements of conductive materials.  We often 
have to conformally coat component pads, component bodies, etc... and to 
avoid voltage creepage along pcb surfaces we add slots cut into the pcb. 
The air is harder to arc across instead of the pcb surface.  We also 
sometimes ADD silkscreen over HV traces for arc suppression, NOT remove it. 
You mention current and voltage in your last sentence.  Again this is for 
high VOLTAGES only.  for higher current we simply make thicker copper or 
wider traces, or both.
Lenny ERG  www.ergpower.com


----- Original Message ----- 
From: "Phil Nutting" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, June 04, 2008 12:33 PM
Subject: [TN] Removing soldermask under SMT devices


As we do more SMT boards with high power or high voltage we have seen some 
failures we suspect are due to flux and other undesirable junk under some 
SMT devices.  In researching cleaning processes (and failures) I have seen 
some articles that show "our fault mode".  One solution seen in this 
research suggests removing solder mask under SMT components to give a larger 
space under the parts to allow the junk to be more easily removed during the 
cleaning process.

Is this an industry problem and is removing the silkscreen under the devices 
an industry solution?  If removing the silkscreen is what folks are doing, 
what are the decision criteria being used as to which components get this 
treatment?  Is it every component or just those that have the highest 
likelihood of failure due to the current through or voltage across the part?

Thanks in advance.

Phil Nutting

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