Have seen failures on boards at environmental test due to current
leakage on some products. Funny thing was it was under SMT electrolytic
capactors (the solder paste was overprinted on the terminations and the
flux wicked under and across the two terminations at reflow) rather than
the real tight standoff parts-some 0603 capacitor arrays (that due to
traces running under the parts had effective standoff heights of 1.2-1.4
mils). In some of the designs we assemble, there are traces running
under components so removing the solder mask is not an option. We had to
revise the cleaning process - qualify another saponifier and revise the
process to run the in line wash conveyor at 0.6-0.8 FPM to give adequate
exposure time to the chemistry and rinse to soften and rinse out the
residues. Ran a DOE and found that the most signficant factors effecting
cleaning were belt speed and wash/rinse temperatures. 


Tom  

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Phil Nutting
Sent: Wednesday, June 04, 2008 12:34 PM
To: [log in to unmask]
Subject: [TN] Removing soldermask under SMT devices

As we do more SMT boards with high power or high voltage we have seen
some failures we suspect are due to flux and other undesirable junk
under some SMT devices.  In researching cleaning processes (and
failures) I have seen some articles that show "our fault mode".  One
solution seen in this research suggests removing solder mask under SMT
components to give a larger space under the parts to allow the junk to
be more easily removed during the cleaning process.

Is this an industry problem and is removing the silkscreen under the
devices an industry solution?  If removing the silkscreen is what folks
are doing, what are the decision criteria being used as to which
components get this treatment?  Is it every component or just those that
have the highest likelihood of failure due to the current through or
voltage across the part?

Thanks in advance.

Phil Nutting

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