Hi Phil
We don't do it, and I'd argue against it.  If you remove the soldermask
under low profile SMT parts, and there are traces under there, then
you've got exposed copper - potentially a disaster, at least a worse
condition than traces covered by soldermask.  If, on the other hand, you
don't have traces under the parts - I wouldn't expect any benefit... 

Would it be possible for you to impose a design rule increasing the
trace to trace spacing for higher voltages traces when under components?

regards,
 - Graham

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Phil Nutting
Sent: Wednesday, June 04, 2008 1:34 PM
To: [log in to unmask]
Subject: [TN] Removing soldermask under SMT devices

As we do more SMT boards with high power or high voltage we have seen
some failures we suspect are due to flux and other undesirable junk
under some SMT devices.  In researching cleaning processes (and
failures) I have seen some articles that show "our fault mode".  One
solution seen in this research suggests removing solder mask under SMT
components to give a larger space under the parts to allow the junk to
be more easily removed during the cleaning process.

Is this an industry problem and is removing the silkscreen under the
devices an industry solution?  If removing the silkscreen is what folks
are doing, what are the decision criteria being used as to which
components get this treatment?  Is it every component or just those that
have the highest likelihood of failure due to the current through or
voltage across the part?

Thanks in advance.

Phil Nutting

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