Then there is the rest of the story - Reliability vs. Survivability Testing
Recently companies are performing survivability testing.
Reliability testing is achieved by assembly and rework simulation followed by thermal cycles to failure at temperatures between 150°C and 210°C. Survivability testing is, simply put, assembly cycles to failure.
Survivability testing is performed where the high temperature is specified between 220°C (tin-lead) and 260°C (lead-free). Our test method specifies starting at ambient then heating to 260°C in three minutes +/- five seconds followed by cooling in approximately two minutes. This type testing is done where the end use environment is so benign as to impose minimal strain and stress. Consider that a high end computer may be designed with a controlled environment where the computer is turned on once in its life and the internal temperature is held constant. For that application the only significant stress is as a result of assembly and rework. A high temperature, highly accelerated test to 220°C produces comparative results in hours.
The other justification for high temperature survivability testing is that the time to results is just hours. Even though the end use environment, for a given application, is not well controlled, one may choose high temperature testing because it has the advantage of a very short time to results. Reliability testing is typically 500 thermal cycles while survivability testing end at 50 cycles. Our reliability test method, for example, produces 500 thermal excursions in two days. High temperature survivability testing allows 50 thermal excursions in about 4 hours. One effect is to increase testing throughput by a factor of ~10:1 if the product is robust and survives to end of test. Weak product fails in just minutes which in effect increased through put by a factor of ~40:1. If there is a failure, standard microscopic analysis demonstrates failure mode and possible causes (thin plating, interconnect smear etc). In the beginning the lot is rejected due violation of IPC requirements base on microscopic examination. Mature users will forgo the cost of microsections and reject on cycle to failure data alone.
There are a few considerations with survivability testing. In survivability testing the failure mode may shift from traditional barrel cracks to corner cracks. It is reasonable to perform survivability testing on a limited sample and if there is a premature failure follow with reliability testing on the balance of the product to better enunciate failure modes and establish a relative reliability ranking. There are a few unique requirements in survivability testing and one is the surface finish cannot have solder as it will reflow at temperatures above liquidous, automatically repairing copper cracks.
For more information please feel free to contact me off line.
Sincerely,
Paul Reid
Program Coordinator
PWB Interconnect Solutions Inc.
235 Stafford Rd., West, Unit 103
Nepean, Ontario
Canada, K2H 9C1
613 596 4244 ext. 229
Skype paul_reid_pwb
[log in to unmask] <mailto:[log in to unmask]>
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Haynes, Kim
Sent: Monday, June 02, 2008 7:04 PM
To: [log in to unmask]
Subject: Re: [TN] Reflow specifications for PCB
Thanks Paul, this is interesting and I appreciate your sharing your knowledge and experience.
Regards,
Kim Haynes
Interface and Clock Products
High-Speed Serial Link Applications
Texas Instruments, Inc.
214-567-2057 Telephone
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Paul Reid
Sent: Monday, June 02, 2008 5:58 PM
To: [log in to unmask]
Subject: Re: [TN] Reflow specifications for PCB
Ok, I admit this is a bit long winded.
If you are not up to this long response just drop down to item #5 below, read that item, my subsequent apology, and then delete the email.
The solder float test (IPC TM 650 2.6.E) has been the standard to prove some degree of bare board reliability after assembly and rework, but the method is proving to be inadequate in today's world particularly with the advent of RoHS requirements for lead free assembly. The solder float method specifies floating a prepared specimen on molten solder, for a prescribed time and number of cycles, followed by a microscopic examination for damage. Although acceptable in the day of wave soldering the use of a reflow oven on high density, high aspect ratio PWBs with high layer counts with inherent increases in mass, at lead-free temperature, had reduce the applicability of the solder float test. It does not adequately reflect the ability of a PWB to survive the rigors of today's assembly and rework.
This problem has been recognized by IPC and at least one committee was organized to investigate alternative test methods to the solder float. I am a member of an IPC committee (D-32 Thermal Stress Test Methodology Subcommittee, 2.6.27) which is chaired by Mike Freda of Sun Microsystems that is reviewing this problem and is in the process of establishing an oven profile to address your concerns. In this response, however, I am not speaking for or as a representative of that committee. This response is a reflection of my personal experiences of assembly and reflow simulation and the effect on PWB (bare board) reliability.
What I would like to do is share some of the experiences my company has in assembly and rework simulation and the ramifications of those types of simulations. PWB Inc. has about 12 years experience in performing assembly and rework simulation and measuring its effect on PWB reliability. Using a representative coupon (IST) we simulate stresses associated with assembly and rework by heating coupons to assembly or rework temperatures in exactly three minutes +/- 5 seconds, followed by cooling to ambient in approximately two minutes. Our method measures changes in resistance to determine if circuits are damaged. Because of the very precise and controlled manor in which assembly and rework simulation is achieved we are able to quantify the effects expressed in failures or damage accumulation due to assembly and rework across a wide range and types of PWBs. Our method has proven to be slightly more aggressive that actual assembly and rework but, as we do not get false positive test results, we consider this a bit of "guard banning".
All that being said here are a few points of interest.
1. PWB reliability is reduced by assembly and rework.
a. Tin-lead assembly and rework can reduce, in rare cases,
reliability up to 25%.
b. Lead-free assembly and rework reduces reliability up to
50% routinely. Many materials are not reliable in lead-free applications.
2. Assembly and rework simulation does not usually cause enough
damage to fail boards out right. Usually the failure develops in the field and is expressed as field failures and failures under warrantee.
3. Some failure modes are very sensitive to assembly and rework and
are expressed as "infant mortality". The infamous "butt joint" failure of skived, sequential laminated boards (typically with no Cu wrap) is one of those failure modes.
4. It is much better to be aggressive in assembly and rework
simulation than to suffer the frustration of false positive results.
Just replicating the exact "defined" assembly cycle is really not adequate. One needs to moderately exceed time, temperature or number of cycles to fail marginal product in any type of assembly simulation.
5. The single most important thing for me to pass on is that prior
to RoHS testing just the copper interconnection reliability was adequate. With RoHS you must test both the copper and material reliability. Delamination artificially extends thermal cycles to failure and is an insidious defect (implicated in CAF) that is hard to find and profound in its effect in PWB reliability.
I apologize for this long winded pontification on the effects of assembly and rework on bare board reliability, but, I suppose, that, though I have the right to express my view, I do not have the right to expect anyone will read the whole response.
Sincerely,
Paul Reid
Program Coordinator
PWB Interconnect Solutions Inc.
235 Stafford Rd., West, Unit 103
Nepean, Ontario
Canada, K2H 9C1
613 596 4244 ext. 229
Skype paul_reid_pwb
[log in to unmask] <mailto:[log in to unmask]>
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Peter L
Sent: Monday, June 02, 2008 2:21 PM
To: [log in to unmask]
Subject: [TN] Reflow specifications for PCB
Hello,
Just wonder if there's a test method that the board shop apply after board fabrication to determine if a PCB meets certain reflow conditions.
Are these "std test" documented in any IPC specs or PCB fab dwg?
Thanks.
Peter
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