Ok, I admit this is a bit long winded.
If you are not up to this long response just drop down to item #5 below,
read that item, my subsequent apology, and then delete the email.
The solder float test (IPC TM 650 2.6.E) has been the standard to prove
some degree of bare board reliability after assembly and rework, but the
method is proving to be inadequate in today's world particularly with
the advent of RoHS requirements for lead free assembly. The solder float
method specifies floating a prepared specimen on molten solder, for a
prescribed time and number of cycles, followed by a microscopic
examination for damage. Although acceptable in the day of wave soldering
the use of a reflow oven on high density, high aspect ratio PWBs with
high layer counts with inherent increases in mass, at lead-free
temperature, had reduce the applicability of the solder float test. It
does not adequately reflect the ability of a PWB to survive the rigors
of today's assembly and rework.
This problem has been recognized by IPC and at least one committee was
organized to investigate alternative test methods to the solder float. I
am a member of an IPC committee (D-32 Thermal Stress Test Methodology
Subcommittee, 2.6.27) which is chaired by Mike Freda of Sun Microsystems
that is reviewing this problem and is in the process of establishing an
oven profile to address your concerns. In this response, however, I am
not speaking for or as a representative of that committee. This response
is a reflection of my personal experiences of assembly and reflow
simulation and the effect on PWB (bare board) reliability.
What I would like to do is share some of the experiences my company has
in assembly and rework simulation and the ramifications of those types
of simulations. PWB Inc. has about 12 years experience in performing
assembly and rework simulation and measuring its effect on PWB
reliability. Using a representative coupon (IST) we simulate stresses
associated with assembly and rework by heating coupons to assembly or
rework temperatures in exactly three minutes +/- 5 seconds, followed by
cooling to ambient in approximately two minutes. Our method measures
changes in resistance to determine if circuits are damaged. Because of
the very precise and controlled manor in which assembly and rework
simulation is achieved we are able to quantify the effects expressed in
failures or damage accumulation due to assembly and rework across a wide
range and types of PWBs. Our method has proven to be slightly more
aggressive that actual assembly and rework but, as we do not get false
positive test results, we consider this a bit of "guard banning".
All that being said here are a few points of interest.
1. PWB reliability is reduced by assembly and rework.
a. Tin-lead assembly and rework can reduce, in rare cases,
reliability up to 25%.
b. Lead-free assembly and rework reduces reliability up to
50% routinely. Many materials are not reliable in lead-free
applications.
2. Assembly and rework simulation does not usually cause enough
damage to fail boards out right. Usually the failure develops in the
field and is expressed as field failures and failures under warrantee.
3. Some failure modes are very sensitive to assembly and rework and
are expressed as "infant mortality". The infamous "butt joint" failure
of skived, sequential laminated boards (typically with no Cu wrap) is
one of those failure modes.
4. It is much better to be aggressive in assembly and rework
simulation than to suffer the frustration of false positive results.
Just replicating the exact "defined" assembly cycle is really not
adequate. One needs to moderately exceed time, temperature or number of
cycles to fail marginal product in any type of assembly simulation.
5. The single most important thing for me to pass on is that prior
to RoHS testing just the copper interconnection reliability was
adequate. With RoHS you must test both the copper and material
reliability. Delamination artificially extends thermal cycles to failure
and is an insidious defect (implicated in CAF) that is hard to find and
profound in its effect in PWB reliability.
I apologize for this long winded pontification on the effects of
assembly and rework on bare board reliability, but, I suppose, that,
though I have the right to express my view, I do not have the right to
expect anyone will read the whole response.
Sincerely,
Paul Reid
Program Coordinator
PWB Interconnect Solutions Inc.
235 Stafford Rd., West, Unit 103
Nepean, Ontario
Canada, K2H 9C1
613 596 4244 ext. 229
Skype paul_reid_pwb
[log in to unmask] <mailto:[log in to unmask]>
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Peter L
Sent: Monday, June 02, 2008 2:21 PM
To: [log in to unmask]
Subject: [TN] Reflow specifications for PCB
Hello,
Just wonder if there's a test method that the board shop apply after
board fabrication to determine if a PCB meets certain reflow conditions.
Are these "std test" documented in any IPC specs or PCB fab dwg?
Thanks.
Peter
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