Don't forget the collateral damage. Not only is the surface finish and
therefore solderability degraded by repeated soldering, the adjacent
interconnect structures and the dielectric material in that area of the
board are also degraded by those same thermal excursions.

It would be a heck of a thing to have a component perfectly soldered,
after the fifth rework, to an open circuit.

How much are the adjacent interconnect structures and dielectric
materials degraded by repeated soldering? ... it depends.

"Survivability" testing of representative coupons may be helpful.

Sincerely,

Paul Reid

Program Coordinator

PWB Interconnect Solutions Inc.
235 Stafford Rd., West, Unit 103
Nepean, Ontario
Canada, K2H 9C1

613 596 4244 ext. 229
Skype paul_reid_pwb
[log in to unmask] <mailto:[log in to unmask]>


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Joe Macko
Sent: Friday, May 23, 2008 1:41 PM
To: [log in to unmask]
Subject: [TN] Methodology for determining the # of reworks ENIG finished
solder lands for leaded components can withstand

Techs,

 

I am looking for some help / guidance on how to analytically determine
the number of times the same leaded component can be replaced on a ENIG
finished board before the solder lands located on the PCB have been
degraded beyond their capability to provide a solderable class 3 surface
(.e., how many times can the ENIG finished solder lands with stand a
rework/component remove & replace).  I suspect the dissolution rates of
nickel and copper come into play however I am not sure how to approach
this issue and suspect there are some relatively straightforward
formulas out there to accomplish this task. Everyone has a different
idea and there are numerous rules of thumb discussed but I would like to
try something more analytical (without having to use a supercomputer).
Thanks again and everyone enjoy the long weekend.

 

Best Regards,

-joe

 


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