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From:
"Terry L. Munson" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, [log in to unmask]
Date:
Fri, 18 Apr 2008 16:35:25 EDT
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Bill
As one of the active task group participants during the 90s when we were  
asked to update the equivalence factors table and using low  solids cleanable and 
no clean formulations,  we found it difficult to  assess these new types of 
low solids residues and if you look at the large  detailed report from the task 
group (IPC TR 583) we found it difficult to  correlate between static and 
dynamic systems.  The use of higher pass fail  criteria were in place for 
automotive users (one in particular used  28 ug/in2 instead of the 14 ug/in2 from 
1978 to 1991 with no field  performance problems related to flux residues with 
mean levels at 21 ug/in2  while using an 18-24% solids RMA flux) that did not 
see problems.  
 
My concern with cleanliness is not the generalized cleanliness of a total  
board but the amount of contamination present between pads, in via's or  
thru-hole devices.  The pocket of contamination below an 0805 capacitor has  created 
drained batteries when the entire assembly tests clean by ROSE and by  bag 
extraction Ion Chromatography. It is only when we look at the localized  pocket 
of contamination do we see the direct correlation to field and  reliability 
performance.  Many of the localized areas we look at with the  C3 tester are 
clean and show low levels of contamination, but when we see the  combined 
processing effects of selective wave soldering using a pallet to  isolate the area we 
find that the residues that can be trapped between the  pallet and circuit 
board (low solids no clean VOC free) are also protected from  the heat but are 
very corrosive due to the water carrier and acidic pH 2.35.  Dendrites are 
growing in these nearby areas, as well as stray voltage problems  and intermittent 
performance issues and No Trouble Found (NTF) returns.  
 
It is important to understand the cleanliness of an assembly but it is more  
important to understand the cleanliness of the processing steps such as 1st  
reflow, 2nd reflow, wave soldering bottom and top side, bare board unsoldered  
areas, micro via's that have fabrication residues trapped inside causing  
performance problems and the hand solder / touch up residues.  This type of  
cleanliness understanding comes from being able to do localized non-destructive  
residue assessment and ion chromatography analysis. 
 
 
Cleanliness testing must predict field performance.  Using localized  testing 
is the only way I am aware of understanding how much contamination is  
present in the areas of critical circuitry that tends to fail earliest. 
 
Terry Munson
Foresite
765-457-8095
_www.Residues.com_ (http://www.Residues.com) 
 
 
 
 
In a message dated 4/18/2008 1:54:54 P.M. Eastern Daylight Time,  
[log in to unmask] writes:

As  perhaps the only person still around that attended the meetings    
resulting 
in the equivalence factors and IPC Cleaning &  Contamination  Chair  at that 
time, perhaps a few points would  facilitate the  discussion:

1. The Navy set up the ionic testing  development program to  solve a serious 
 
failure problem in S.E.  Asia. 
It worked.

2.  In the timeframe when the test was  developed and put in place by the   
military, most of the rest  of the electronics industry in the US used the  
mil  
specs  since they were free.

3. As the IPC set up and  adopted Classes  1-3 (basically toys up to  
military/high rel), I asked  the  committee if we used the mil test result 
for 
Class 3, 
could we  use  1.5x that limit for Class 2 and 2-3x for Class 1? 
The response  was that with  proper cleaning, the mil limit could readily be  
 
achieved while serving  to monitor daily production. So the industry  
continued 
to  use the  (free) mil spec test  standard.

4. The ionic contamination test was a  valuable  monitoring tool, since  the 
SIR tests were done on coupons,  not  on actual assemblies, and took 1-2 
weeks 
to 
complete. Needless  to  say, a high volume electronics producer could turn 
out 

a  significant  volume of PWAs during that time, often shipping them into  
the  
field as  soon as assembly was completed.

5. As  noted in my SMT column (offered  yesterday) T. O.  Duyck of Northern  
Telecom was charged with  implementing water soluble flux for   NT 
electronics 
production. During  that time he observed and reported  the  differences in 
flux 
residue  release rates, pointing  out that rosin ca 90% of  rosin flux 
residues  
release from  the PWA surface during the 10-15 test time for  ionic test   
equipment, while water soluble flux residues may take up to 2 hrs.  to   
achieve the same 
level of release. Thus the release  rate should be checked  to  ensure the 
flux 
used, time test  time and the instrument employed  provide  reliable results 
and  guidance to the production engineer. 
(See T. O. Duyck and M. Boulos,  "Water Washes  Reliability into Telephone 
Circuit Packs", IPC-TR-206,  April, 1978)
Based on this work, I investigated the release rate of   SA flux residues, 
finding it even faster than rosin fluxes. (See W. G.  Kenyon,  "Synthetic 
Activated (SA) Flux Technology: Development,  Commercialization,  Benefits 
and Future 
Applications", Internepcon  Japan, 24 Jan.  1986)

6. In the late 1980's, the materials and  acceptance of the  no clean or low  
residue or acceptable dirt  concept became widely  accepted and implemented 
on 
the  designs  of the time. Outsourcing to  contract assemblers (both in the 
US 
and  
overseas) became widely practiced,  so much of the former 'in-house'  
cleaning 
expertise disappeared. 

7.  This was seen at IPC as  the number of company sponsored volunteers   
dwindled. Could we  take on projects today to develop an updated ionic test  
for   pr
ocess monitoring? Find enough participants to conduct   statistically sound  
round 
robin testing?   

Bill   Kenyon
Global Centre Consulting
3336 Birmingham  Drive
Fort Collins,  CO  80526
Tel: 970.207.9586    Cell:   970.980.6373




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