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Date: | Mon, 24 Mar 2008 17:14:57 -0400 |
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Hi Werner,
I find that grid size as an influence in delamination surprising also. This has been seen in our testing and a number of our customer's testing as well . Grid sizes below .040" and above .020" is significantly more prone to delamination.
I have mentioned the "false positive" PWB reliability results possible with delamination before in a couple of papers. Bill Birch and I have both brought this phenomenon up at a number of IPC and SMTA meetings.. Mostly delamination extends reliability cycles to failure; rarely it reduces cycles to failure. That is why we feel delamination evaluation is as important as reliability testing in a lead-free application.
The delamination may occur during preconditioning or develop during thermal cycling.
The data you reference below is normalized to 500 cycles but we have seen this trend over and over in lead-free testing. We have seen that trend, in lead free reliability results for years and that is one of the reasons Bill and Jason develop "DELAM" test method to find delamination electrically. We are beginning to be able to quantify delamination and the effect on reliability testing.
One interesting thing I have noticed is with stress relieving delamination, the delamination does not align with barrel cracks. With stress focusing delamination the delamination frequently ends at barrel cracks that are wide and gaping.
Paul
________________________________
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Thursday, March 20, 2008 8:13 PM
To: Paul Reid; [log in to unmask]
Subject: Re: [TN] How much stress is needed?
Hi Paul,
I do not find grid size as major influence surprising, since it has been shown both analytically and experimentally, that closely spaced vias support each other.
However, I have a real problem understanding why PCB delamination should act as a stress relief for the via barrels. I cannot think of any physical mechanism that would do this-I would guess that there is something else going on in addition to or as an underlying cause of both the delaminations and the increase cyclic life.
How about this: initially, high vapor pressure cause the PCB delamination and is driven out of the resin matrix resulting in subsequent more benign loading conditions. That should however also work in favor of the 3x260C preconditioning.
The results you show-and I assume the thermal cycles are all the same:
Coupons tested "as received" achieve 500 thermal cycles to failure (end of test).
Coupons precondition 3X230°C (tin/lead assembly simulation) achieve 400 thermal cycles.
Coupons precondition 6X230°C (tin-lead assembly and rework) achieve 300 thermal cycles.
Coupons precondition 3X260°C (lead free assembly) achieve 350 thermal cycles.
Coupons precondition 6X260°C (lead free assembly and rework) achieve 500 thermal cycles,
make perfectly good sense until "Coupons precondition 6X260°C (lead free assembly and rework) achieve 500 thermal cycles"-that makes no sense whatsoever.
Somewhere in your statement "Once in awhile delamination in a group of coupons will reduce the cycles to failure by ~50%, but most of the time delamination produces a false positive result by extending cycles to failure. We differentiate delamination as either stress relieving or stress focusing in a give PWB build" is the likely clue to this puzzle.
Werner
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