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February 2008

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Subject:
Re: Revision levels of PCB Assy v-v PCB Fab
From:
"Maisch, John" <[log in to unmask]>
Reply To:
(Designers Council Forum)
Date:
Wed, 13 Feb 2008 10:03:27 -0500
Content-Type:
text/plain
Parts/Attachments:
text/plain (71 lines) 
Gary,

You might take a look at IPC-D-325, which deals with PWB Assy documentation; particularly the section
that deals with Revision Level Control (RLC).

Hope this helps,

John Maisch jr
PWB Design Group Leader

Formation, Inc.
121 Whittendale Dr.
Suite A
Moorestown, NJ 08057-1365
phone: 856-380-2920 or 856-234-5020 x2920
fax: 856-234-5242



-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]]On Behalf Of Gary
M. Koven
Sent: Wednesday, February 13, 2008 9:10 AM
To: [log in to unmask]
Subject: [DC] Revision levels of PCB Assy v-v PCB Fab


Thirty-some odd years ago when I was a novice designer, I was trained that
the revision level of a PCB assembly (PCBA) must match, or be greater than,
the revision level of the bare PCB fab.

We have a situation now with usable Rev 5 bare board glass that is being
populated for a different application, requiring a new part number for the
PCBA and the BOM.

I'm inclined to do the initial release of the new PCBA and BOM at Rev 5,
based on experience.  My boss wants a Rev 0 release.

I can't remember what document originally specified the form, fit and
function rules for PCB and PCBA revision level control.

Can someone provide hard copy evidence for revision level control to
substantiate, or disprove, what I was taught back in the day?

Thanks and Best Regards,

----------------------------
Gary M. Koven, C.I.D.
Dynazign, Inc.
Charlotte, NC, USA
704.405.1234
Veteran of the Marsh School

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