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January 2008

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Subject:
From:
Richard Kraszewski <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Richard Kraszewski <[log in to unmask]>
Date:
Thu, 3 Jan 2008 15:35:46 -0500
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Following Doug's lead....

As a contract manufacturer, my organization constantly gets asked the
same question by some customers who don't have a clue and ask that we
propose something to them.  This of course is rather difficult because
of the ever present "well it depends" on what you're making and what
type of technology you have on the assembly. Presently, not much out
there in terms of useful industry specifications.  The ROSE requirements
set fourth in J-std-001 are too stringent for some and too lax for
others, depending on what you're building and the final device
environment.  Also you have the ever present issue of the ROSE taking a
cleanliness "average" that could still leave you with more than enough
ionics at a critical location to induce failure.

While not perfect by any means, the Ion chromatography test method and
limits set fourth by FORESITE labs seems to make the most sense to
myself and internal company team.  You can get that table off the their
web-site or by contacting them there and requesting it. 
 

Rich Kraszewski / Kimball-GTS
847-621-7310
 
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Douglas O. Pauls
Sent: Thursday, January 03, 2008 11:48 AM
To: [log in to unmask]
Subject: Re: [TN] specifying board cleanliness

Well, then, we have a heffalump of a whole different color.  See, when 
someone says "boards" to me, there are no components.  When someone says

"assemblies" they have components. 

So, then, is your basic question "What kinds of language do I put in my 
procurement documents, using IPC test methods, that give me clean 
assemblies coming from my contract manufacturer"?

Doug Pauls




Phil Nutting <[log in to unmask]> 
01/03/2008 11:31 AM

To
"[log in to unmask]" <[log in to unmask]>
cc

Subject
RE: [TN] specifying board cleanliness






Doug,
 
I forgot in my original e-mail that I'm concerned with populated boards.

So I'm guessing there is a different document for that.  The tests are 
listed in IPC-TM-650, but my eye glass over when I try to decipher
these. 
I know designing by thumb nail is a bad practice, but what is there for
us 
who are practically laymen?
 
Thanks,
 
Phil

From: [log in to unmask] [mailto:[log in to unmask]] 
Sent: Thursday, January 03, 2008 10:02 AM
To: Phil Nutting
Subject: Re: [TN] specifying board cleanliness


And, here is the 5701 I referenced. 

Doug Pauls




Phil Nutting <[log in to unmask]> 
Sent by: TechNet <[log in to unmask]> 
01/03/2008 08:44 AM 

Please respond to
TechNet E-Mail Forum <[log in to unmask]>; Please respond to
Phil Nutting <[log in to unmask]>



To
[log in to unmask] 
cc

Subject
[TN] specifying board cleanliness








Good Morning and Happy New Year to All,

Let me start by confessing my ignorance relative to cleanliness of
circuit 
boards.  We have no idea what numbers to specify that fit into the IPC 
testing methods for board cleanliness.  If I tell my CMs to make the 
boards clean, it would be good to specify a target value and or test 
method.

Can someone give me some guidance on how to chose these specifications? 
What are worth while tests and which ones are window dressing?

I've read through some of the IPC tests methods and my head hurts.

Thanks in advance,

Phil Nutting

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Note: All the information contained in this e-mail and its attachments
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proprietary to Kaiser Systems, Inc. and it may not be reproduced without

the prior written permission of sender. If you have received this email
in 
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