Steve, man it is good to hear you are still around in the industry. I
have thought of you and many of the other folks from NAWC (NAC) through
the years. Hope all is good and well with you, Jon
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Sauer, Steve
(Xetron)
Sent: Tuesday, January 22, 2008 2:22 PM
To: [log in to unmask]
Subject: Re: [TN] Solder thieves
Ioan,
Back when I was still doing wave soldering of SMDs (10+ years ago at a
former employer), I found an IC Package Databook published in 1995 by
Philips Semiconductors provided several options for SOICs (including
SSOPs and TSOPs) and QFPs. I created a test panel with variations of
the suggested footprints and was able to determine the best footprint
based on yield. I tried a quick search on the website but only found
this document that has the options for wave soldering of SOICs (the QFP
info isn't there)
http://www.nxp.com/acrobat_download/various/SC13_MOUNTING.pdf
Hope this helps.
Steve Sauer, CEPM
Senior Project Engineer
Northrop Grumman Xetron
Cincinnati, OH
513-881-3368
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Ioan Tempea
Sent: Monday, January 21, 2008 2:48 PM
To: [log in to unmask]
Subject: [TN] Solder thieves
Dear Technos,
Is there any standard setting the specifics (size, count, position with
respect to the active pads) of solder thieves used for reducing the
incidence of solder bridges at wave soldering?
Thank you,
Ioan
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