Also, if you go back to the IPC Review, October or November 2000, I did a
review of bare board cleanliness provisions in IPC specifications and mil
specs. I have it in PDF or you can get it from IPC.
Doug Pauls
Tom Newton <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
01/03/2008 10:36 AM
Please respond to
TechNet E-Mail Forum <[log in to unmask]>; Please respond to
Tom Newton <[log in to unmask]>
To
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cc
Subject
Re: [TN] specifying board cleanliness
Phil and All:
I routinely stay out of TechNet discussions. However, just to clarify
what Graham correctly provided earlier on the currently accepted ionic
contamination level per IPC documentation (1.56 micrograms per square cm
of NaCl equivalent), it should be noted that the bare (unpopulated) PCB
specification (IPC-6012) defines this same contamination value in
section 3.9.1 "Cleanliness (for bare boards) Prior to Solder Resist
Application".
If you have further questions pertaining to bare printed boards, please
examine this document, as it contains a wealth of requirement values for
this product.
Tom Newton
IPC
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Graham Collins
Sent: Thursday, January 03, 2008 9:10 AM
To: [log in to unmask]
Subject: Re: [TN] specifying board cleanliness
Happy New Year Phil!
Well, "it depends"...
First question is how clean do you need them to be? Depends on the
application and environment. Second question is what sort of assembly
process the CM is using - if "no clean" then they will be justifiably
opposed to cleanliness testing.
The generic callout that we most commonly see on drawings is "clean per
J-STD-001 C-22" - which translates into clean the assembly, both sides,
and then do an ionic contamination test with a upper limit of 1.56
micrograms / cm2 NaCl equivalent contamination. I'm not sure why
J-STD-001 gives an option to only clean one side - never seen that
process in use. Anyway, a starting point...
regards,
Graham Collins
Halifax Production Engineering
L-3 communications Electronic Systems
(902) 873-2000 ext. 6215
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Phil Nutting
Sent: Thursday, January 03, 2008 10:45 AM
To: [log in to unmask]
Subject: [TN] specifying board cleanliness
Good Morning and Happy New Year to All,
Let me start by confessing my ignorance relative to cleanliness of
circuit boards. We have no idea what numbers to specify that fit into
the IPC testing methods for board cleanliness. If I tell my CMs to make
the boards clean, it would be good to specify a target value and or test
method.
Can someone give me some guidance on how to chose these specifications?
What are worth while tests and which ones are window dressing?
I've read through some of the IPC tests methods and my head hurts.
Thanks in advance,
Phil Nutting
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