At 04:24 AM 12/12/2007, Mark F. Focht wrote:
>I have a design that,due to space constraints, requires stacking microvias 
>(L1-
>L2) directly on top of (in line with) drilled buried vias (L2-L7, 
>L2-L11).  I am
>receiving conflicting information about this strategy being reliable (storage
>temp. range -50C to 110C, operating temp. range -40C to 85C) because of
>the different CTE's of the via fill material used in the L2-L7/L2-L11 vias 
>and
>the board material (FR406, 170Tg). While the board shops that will fab this
>admit they prefer the vias be staggered (not very pratical in this 
>design), they
>claim they have produced boards of this type without negative feedback or
>issues.  The CM that will be assembling this is extremely hesitant about 
>using
>this via strategy.  Does anyone have experience using a stack-up similar to
>this?  Is there a plugging paste material that very closely matches the 
>CTE of
>FR406, 170Tg?  Any and all comments are welcome.

Do a lot of it.  Regarding buried via fill, the best IST performance and 
solder shock survivability I've seen has come with the San Ei paste. 
Clearly superior to the MacuVia and Peters.  Taiyo is showing up now but 
jury still out -- incomplete test results. Had good luck in IST on lower 
aspect ratio 2+4+2 (1mm overall thick) qual w/ the Taiyo.


>Thanks,
>
>Mark Focht C.I.D.+
>Pole/Zero Corporation
>5530 Union Centre Dr.
>West Chester, Oh  45069-4821
>
>Voice:  513.870.9060 X173
>FAX:    513.870.9064
>Email:  [log in to unmask]
>
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