Ionics by SEC test should be less than 1ug NaCl/cm^2
* after oxide
* before soldermask
* after final surface finish
Should be tested at least once per shift at all 3 process points. If you're
using standard laminate they don't have to do it on your actual product as
long as it's part of their daily/shift monitor disciplines.
However, it's prudent to specify the test be done on your actual lot if
you're using something other than the standard material run in the
particular fab (e.g. a specialty laminate such as a ptfe/ceramic blends
from Rogers, Arlon, Taconic et al).
dw
At 10:10 AM 11/22/2007, Sherif Refaat wrote:
>Jack;
>
>IPC-6012 Paragraph 3.10.3 reads "Cleanliness of Inner Layers after oxide
>treatment prior to lamination When specified, inner layers shall be
>tested per 3.10 and meet the requirements of the procurements documentation."
>
>Par. 3.10 calls for solvent extract method to measure cleanliness.
>
>Sherif,
>
>----- Original Message -----
>From: "Jack Olson" <[log in to unmask]>
>To: <[log in to unmask]>
>Sent: Thursday, November 22, 2007 11:28 AM
>Subject: Re: [TN] Core Quality Issue?
>
>
>I don't know what the base material is, but I'll ask on Wednesday.
>
>We have a big meeting scheduled on Wednesday with the middleman
>who is "managing" the vendor in Taiwan. Haven't heard from the actual
>vendor yet. I don't even have a contact I could call, believe it or not!
>
>I just wanted to be as prepared as I can be for Wednesday, because
>this type of discussion is not my cup of tea...
>
>We had a company called Foresite do some analysis, who reported
>internal uncleanliness, the middlemen says we never specified anything
>about internal cleanliness (believe it or not!) and I was just wondering
>if there might be a problem with the core material itself, which would
>mean the boards are screwed before they even start, right?
>
>but while I'm thinking about it,
>Does IPC have any statements about internal cleanliness?
>
>I will cheerfully supply more details after Wednesday if I'm not bogging
>down the list too much...
>
>Jack
>
>
>On Nov 22, 2007 2:23 AM, arnaud grivon <[log in to unmask]> wrote:
> > Jack,
> >
> > As others said, PCB manufacturing quality could have been more easily
> > suspected if the filamentation originated from a PTH.
> > In your case, it looks like you have evidences of copper both in
> > pre-preg and inner cores.
> > Assuming the base material is the same for pre-pregs and cores, I would
> > rather lean towards a material problem.
> > ...which makes me come back to my initial question from your previous
> > post: what is the base material used for that PCB?
> > Best regards,
> >
> > Arnaud Grivon
> >
> > Jack Olson a écrit :
> > > Sorry to re-start a previous discussion, but I'm still dealing with a
> board
> > > failure and I'm trying to learn fast.
> > >
> > > I received a higher-resolution picture of a board problem we are having
> > >
> > >
> http://www.frontdoor.biz/PCBportal/corequestion.jpg<http://www.frontdoor.biz/PCBportal/corequestion.jpg>
> > >
> > > and if I look at it closely, I can see the dividing line between all ten
> > > layers of dielectric.
> > >
> > > By looking at which way the copper is located from each dividing
> line, I can
> > > tell which are cores and which are prepreg (because the prepreg
> layers will
> > > flow "around" the copper features)
> > > For example, the thin pinkish layer is a core. Am I on the right track so
> > > far?
> > >
> > > So, our problem is a 120V end-of-line test frying two out of every
> hundred
> > > boards right through the pinkish core material with the white streak
> through
> > > it
> > > (3.2 mils, which should handle a few kilovolts at least, right?)
> > >
> > > So here's the question:
> > > Should I be questioning the material quality rather than the bare-board
> > > manufacturing process itself?
> > >
> > > I realize you guys have already been generous with helping me on
> this, so I
> > > hope I'm not pushing your patience...
> > >
> > > onward thru the fog,
> > > Jack (aka "the new guy")
> > >
>
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