January 2008 is right around the corner - get questions answered on the
latest hot topics and current issues at the forefront of electronics!
All of these workshops are being offered in the sunny city of San Jose,
CA!
PD-01: Advanced Troubleshooting for Printed Wiring Board Manufacturing -
Defect Analysis and Prevention
January 15, 2008 - San Jose, CA
8:30 am - 11:30 am
Instructor: Michael Carano, Electrochemicals, Inc.
What are the critical success factors for a defect-free PWB fabrication
process and maximum long-term reliability? This course tackles the
answers! Join us for this half-day workshop and gain the
process-technology know-how you need to improve the yield, quality and
reliability of complex printed wiring boards. Emphasis is on identifying
and preventing defects with respect to electroless copper and direct
metallization, electroplating, drilling and multilayer fabrication.
PD-02: Via Filling Technology and Processes
January 15, 2008 - San Jose, CA
1:00 pm - 4:00 pm
Instructor: Michael Carano, Electrochemicals, Inc.
Attend this course for insights on the technological drivers behind the
need for highly effective, reliable via filling in high-density,
high-aspect-ratio printed wiring boards. The course pays close attention
to the use of via filling materials for highly complex circuit designs.
PD-03: Fundamentals of Printed Circuit Technology - Materials and
Manufacturing Processes
January 16, 2008 - San Jose, CA
8:30 am - 11:30 am
Instructor: Joseph Fjelstad, Silicon Pipe, Inc.
This half-day course provides a comprehensive overview of this
indispensable technology. It reviews the materials and processes that
comprise the wide array of electronic interconnection substrates used
today and why they were chosen. You will learn about multilayer, metal
core, embossed, flexible and rigid flex circuits and more. Discussions
will also include newer HDI/microvia and embedded passives technologies,
new PCB design concepts and a brief look at the impact of lead free on
PCB manufacturing.
PD-04: Design Principles for BGA and CSP Technology Implementation
January 16, 2008 - San Jose, CA
1:00 pm - 4:00 pm
Instructor: Vern Solberg, Tessera Technologies, Inc.
This workshop is based on the latest version of the IPC-7095 document,
Design and Assembly Process Implementation for BGAs, and covers both
wide and fine-pitch BGA packaging methodology. The information will
focus on IC packaging standards, review qualification requirements and
study land pattern geometry alternatives, circuit routing guidelines as
well as important factors related to high density PCB fabrication
technologies, assembly process development, inspection criteria and
solder quality assessment.
This is your chance to gain valuable knowledge on these hot topics!
Register by December 21 and receive a 10% discount or register three
individuals from your company at the same time and receive the fourth
registration FREE. For more information or to register, please cut and
paste www.ipc.org/AdvTr0108 into your browser and download the
registration form.
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