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November 2007

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Subject:
From:
Bill Haas <[log in to unmask]>
Reply To:
(Leadfree Electronics Assembly Forum)
Date:
Thu, 1 Nov 2007 21:30:14 -0600
Content-Type:
text/plain
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text/plain (142 lines)
Werner,

 

Many thanks for sharing your wisdom here.  

 

My 9701 was down-level, so today I obtained 9701A and read through it to see
what I could learn.  

 

I'm trying to understand the difference between CTE and creep rate, and how
this relates to dwell time in my thermal cycle test.  Please pardon my
elementary education in this area.

 

Let me see if I understand correctly.  CTE tells me that I will arrive at a
certain place from where I am now with a certain change in temperature.
Creep rate tells me how long it will take to get there, right?  Under field
conditions, I assume there would usually be plenty of time for the device to
reach full relaxation into the new temperature condition, thus arriving at
the certain place dictated by CTE and temperature.  But in my test if I turn
around and go the other direction before my device ever gets to the
destination, my test would seem to be compromised.  It would be like
starting out in Omaha with a ticket to New York and then Los Angeles, and
never making it past Detroit and Denver, wouldn't it?  And therefore I would
never experience the extremes of deformation, of creep-fatigue damage, that
the device would see in the field per thermal cycle.  

 

IPC 9701 says use a 10 minute dwell, same as 9701A, with temperature ramp
rates less than 20 degrees C.  I understand that neither prediction of
accelerated test results nor product reliability extrapolation from thermal
cycle test results is possible given the lack of validated models.  But we
do know a fair amount about the thermal cycles the device will see in the
field (9701 table 3-1 seems to do a good job of estimating this), and from
this knowledge I can make a fairly educated guess at the number of thermal
cycles I need to run as a representative test (~1:1 + safety margin).  But
what I'm wondering is whether the ramp rate and dwell I'm using get me in
the vicinity of New York and LA, or whether I'm fooling myself as I meander
in the Midwest, never experiencing the stress and strain of the coasts.  I
might think I will live longer that I should reasonable expect from my test
results, once I actually start traveling the whole distance and staying
weekends.

 

Is 10 minutes enough dwell with LF solder, and say an 18 degree C per minute
ramp rate, to make it to the coasts?  If I only dwell for 5 minutes, is
there a percentage I could apply to "de-rate" the test strength, to estimate
how far I have taken the device?  (Feel free to tell me to just do the test
over again and next time do it right.)

 

One last elementary question:  higher modulus of elasticity means less
elastic, less able to recover to original condition once stimulus is removed
or reversed, therefore more stressed, right?

 

Once again, I appreciate your remedial tutoring for this slow student.

 

Regards,

 

Bill

 

 

 

 

  _____  

From: [log in to unmask] [mailto:[log in to unmask]] 
Sent: Wednesday, October 31, 2007 11:01 AM
To: [log in to unmask]; [log in to unmask]
Subject: Re: [LF] Thermal Cycle Test and CTE

 

Hi Bill,
What I said in 1994, and many times before and this that date, still holds
even-or perhaps more so-for Pb-free solders.
Ahh, the vicissitudes of the Pb-free idiocy.
The problem is less so with reliability predictions for product in the
one-cycle-a-day arena, in both the cases of SnPb and the SAC-flavor of the
month the creep process is complete at the operating temperatures and
essentially complete in the off-state (room temperature). My tentative
recommendation for product reliability is to use a model developed for SnPb
[that expressly excludes straight Coffin-Manson and Norris-Landzberg] and
use a safety factor of about 3. That can be fine-tuned as actual field
reliability data become available [beware of the billions of Pb-free solder
joints claimed; this is not data, is anecdotal at best (or at its worst) and
for throwaway products].
Recent data at various conferences show that SAC solder joints perform equal
to or somewhat worse than control-SnPb solder joints in accelerated testing.
Side-by-side accelerated testing will always show a higher stress range for
SAC solder joints [higher modulus of elasticity] and a smaller strain range
[much slower creep rates] as compared to control-SnPb solder joints. So
depending on test environment and test arrangement, the hysteresis loops
being the measure of the cyclic visco-plastic strain energy and thus
creep-fatigue damage, will be more or less the same.
Because we do not have acceleration models for SAC solders, prediction of
accelerated test results is not possible at this time. Nor for that matter
is extrapolation to product reliability from the results of accelerated
testing [that is the reason that IPC-9701A is not a performance standard for
Pb-free solders].
QUESTION: "Would someone please say again what the dwell time at extremes
should be for lead-free solder systems in order to experience the full CTE
hysteresis loop?
ANSWER: We do not know enough do give an answer to this question-but see the
3rd paragraph above for a practical answer.

Esteemed or otherwise,
Werner



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