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October 2007

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Subject:
From:
"Brooks,Bill" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Brooks,Bill
Date:
Wed, 3 Oct 2007 16:48:57 -0700
Content-Type:
text/plain
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text/plain (288 lines)
John, 

Way cool!   :)

It's reassuring to see someone has been down this road and worked the bugs
out of the process... 
Thank you!

Do you suppose that thicker plating in the holes would help the situation?
Is there a practical limit to how much plating can be added to the barrel of
the thermal vias? I'm planning on pumping about 8 watts of heat thru the
thermal vias on a high volume RF board I am doing... 

Best regards,


Bill


-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]] 
Sent: Wednesday, October 03, 2007 3:35 PM
To: TechNet E-Mail Forum; Brooks,Bill
Subject: RE: [TN] Thermal vias and plugging ...

I used to work in a place with a very high wattage output amplifier
and a thermal paddle. The mechanical guy was so convinced that the solder
would just run down the holes that we forced our fabricator to develop
a plugging process which was flush with the surface. After much agnst
they developed a process that plugged the vias, then the vias where sanded
flush so there was no annualar ring at all. Remember this was 10 years ago.
So now we have thermal paddles the vias are filled sanded flush with the
copper and the
hasl covered copper all around. After about 5,000 units we realized
that we were getting voids under these thermal pads. Our theory was that
yes the via was plugged but there was about 1 to 2 mils of area on top
of the via to the edge of the hasl. So we really had these little cups with
each via. Our conclusion was that this was trapping air and causing the
problem
so we started looking for a plate over process. In the meantime a new
mechanical
guy hired in and took one look at the thing and did some calculations and
said
you don't need to plug these vias at all. The surface tension will stop the
solder from running down the holes. Sure enough we stopped plugging the
holes
the paste did not run out and all of our soldering problems went away.
His calculations were based on the surface area versus the volume of the via
cylinder and how close the thermal pad was to the board.  I have done a lot
of thermal pads and just left the vias open on both sides and have had no
problems with runout. But I would imagine every case is different. In our
case we were using 12 mil holes in a .062 thick board and it was important
that
the termal pad was making contact with the paste. But we built about 40,000
units
after that with no problems. 

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Brooks,Bill
Sent: Wednesday, October 03, 2007 11:51 AM
To: [log in to unmask]
Subject: [TN] Thermal vias and plugging ...


Well this is a little different sidetrack but still connected to vias and
filling... but if you are attempting to make 'thermal vias'... what is the
most reliable and economic way to accomplish it and successfully get the
heat out under a part that has a thermal 'belly' pad? 
The issues I am aware of are related to the solder paste melting into the
vias at reflow ... its touchy to do because the vias if left open tend to
'steal' the solder from under the part... sometimes causing insufficient
solder in the joint. 
Are fabricators and designers using a some special compound to fill the
vias? Something like loaded thermal epoxy? Is there any data on the subject
that I can read? Or someone to talk to that has some experience with the
issues? 
Cost and performance are things we try to balance... especially when the
customer buys the 'must work but I don't want to pay that much' option... 
:)


Bill


-----Original Message-----
From: Ted Tontis [mailto:[log in to unmask]] 
Sent: Wednesday, October 03, 2007 10:37 AM
To: [log in to unmask]
Subject: Re: [TN] Via plugging with LPI soldermask...

As I understand it you can not use LPI solder resist to plug a via or insure
a via is %100 plugged. You have to you some type of filler if you require a
via to be plugged.  
I have seen some of those threads regarding links between conductive epoxy
and via barrel failure. Is there any data that suggests that conductive
epoxies or fillers shouldn't be used at a specific aspect ratio? What are
the chances that the conductive epoxy is increasing hole wall pull away,
damaging the barrel? Can non-conductive fillers act as an insulator when it
comes to heat transfer within the barrel?

Ted   

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Werner Engelmaier
Sent: Wednesday, October 03, 2007 11:24 AM
To: [log in to unmask]
Subject: Re: [TN] Via plugging with LPI soldermask...

There is no reason why voids in non-conductive fills in PTVs are a 
problem. Kim's experience makes sense.

Werner

-----Original Message-----
From: Haynes, Kim <[log in to unmask]>
To: [log in to unmask]
Sent: Wed, Oct 3  12:12 PM
Subject: Re: [TN] Via plugging with LPI soldermask...

I hve watched this plug/tent discussion thread with interest.  I design
and build boards for multi-gigabit transmission rates in a lab
environment.  When I use conductive filling, I seem to have via problems
during thermal cycling device analysis.  When I use a non-conductive
epoxy, I do not have the problems.  I have not been able to prove this
hypothesis but I think the conductive fill has a different expansion
rate than the board and the small vias tend to crack.  The
non-conductive epoxy expands at about the same rate as the boards and I
do not seem to have the same failure rates from via cracking.  One of my
board fab shops is mil qual rated and they claim that the govt
inspectors do not even want conductive epoxy in the buildings.  It makes
them nervous because it could be used instead of the non-conductive
filler and they do not want any boards with silver epoxy.  I have been
searching to see if anyone has done controlled tests of conductive epoxy
versus non-conductive epoxy fills for via in pad technology.
Thanks,
Kim Haynes
Interface and Clock Products
High-Speed Serial Link Applications
Texas Instruments, Inc.
214-567-2057  Telephone


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Ted Tontis
Sent: Wednesday, October 03, 2007 10:20 AM
To: [log in to unmask]
Subject: Re: [TN] Via plugging with LPI soldermask...

Bill,
    I used to specify in my manufacturing notes 'vias must be
plugged using LPI solder resist' I was told more then one once and from
different suppliers that they could not guarantee the vias would be 100%
'plugged'
using LPI. They would however guarantee that there would be LPI in the
via hole or that the LPI would tent over the via, leaving a void in the
center.
If I required 100% via fill I would have to require that they fill the
holes with some type of conductive filler.

Thank you,

Ted T

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Brooks,Bill
Sent: Tuesday, October 02, 2007 3:44 PM
To: [log in to unmask]
Subject: [TN] Via plugging with LPI soldermask...

Just a quick question...

When specifying 'plugged' vias using LPI soldermask... what is the
actual process used to accomplish this procedure? How do you make sure
the vias are plugged and what is the proper acceptance criteria used to
verify and inspect the finished results? What is an acceptable plugged
via vs. a reject? Is there a spec or standard that spells this out
process and inspection criteria and method for reference?

Thanks in advance...


Bill



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