John

The parameter of importance here is the annular ring defined by the drill 
size, the position of the copper along the edge of the innerlayer and the 
minimum clearance allowed by the electrical requirements imposed upon the 
board. Generally, a there should be at least a 6 mil annular ring in the 
design between the innerlayer and the drilled hole wall, but this requires 
very good process control (better than most commercial fabricators. Most fab 
houses have data showing their probability of success (which translates into 
yield) for various annular ring sizes. I would request this data and design 
accordingly.

Best regards

Lee

J. Lee Parker, Ph.D.
JLP Consultants LLC
804 779 3389


----- Original Message ----- 
From: "John Burke" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, October 15, 2007 4:44 PM
Subject: [TN] Inner layer spacing for reliability


> On an allied question to the one on inner layer for voltage what is the
> minimum drilled hole to copper inner layer clearance?
>
> I have an engineer wanting 6 mil drill to copper nominal which would,
> allowing for a 2 mil drilling tolerance give 4 mil drill to copper on the
> internal layer.
>
> I might be off track but to me that is too close even though the voltage 
> is
> a few volts (crazing, wicking issues etc).
>
> What are experiences on this type of high density close drill to copper
> clearance especially with lead free process temperatures?
>
> Inputs gratefully received,
>
> John
>
>
> John Burke
>
> (408) 515 4992
>
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