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October 2007

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Subject:
From:
"Creswick, Steven" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Creswick, Steven
Date:
Wed, 17 Oct 2007 05:55:51 -0400
Content-Type:
text/plain
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text/plain (48 lines)
Inge,

Can not provide you with any insight/suggestions.  

However, you should have said, "I know there are many OTHER odd
characters among TNetters"

Sounds like an interesting challenge, however.

Steve

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Hernefjord Ingemar
Sent: Wednesday, October 17, 2007 3:09 AM
To: [log in to unmask]
Subject: [TN] JPL Publication 96-25

 Anyone happen to have a newer version of 'GaAs MMIC Reliability
Assurance Guideline for Space Applications'? My old version is 221 pages
and released December 15, 1996. Little too old.
I had some friends at NASA, but that was years ago. I need some help for
analysis of intrinsic failures on PHEMTs. 

By the way, anyone who knows a method for removing ground rails over FET
channels? Wet etching won't work, because it takes gate fingers too. Ion
etching would work but is too expensive and too slow. Plasma etching
will take everything, not only rails. Any genious out there?

Not exactly a PWB matter, but from experience, I know there are many odd
characters among TNetters.

Hopefully
/Inge
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