That may be the specified limit, but 1200 V/mm is one helluva gradient. 
I certainly would not tolerate such a gradient for high-impedance 
applications. I went as low as 25 V/mm when working at impedances of 
 >1E12 ohms with FR-4.

So, to plagiarise an outstanding contributor to this forum, I would say, 
"it depends".

Brian

McGlaughlin, Jeffrey A wrote:
> Phil -
> 
> IPC-2221 Table 6-1 covers electrical spacing column B1 applies to bare
> boards internal traces. The calculated spacing  for 600V would be 0.5mm
> [0.020"].
> 
> 
> Jeffrey McGlaughlin, CID 
> Engineering Designer 
> Battelle 
> 505 King Avenue 
> Columbus Ohio 43201-2693 
> (614)424-7582 Phone 
> (614)458-7582 Fax 
> 
> 
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Phil Nutting
> Sent: Monday, October 15, 2007 10:29 AM
> To: [log in to unmask]
> Subject: [TN] inner layer spacing for voltage
> 
> Good morning,
> 
> One of our engineers posed this question;
> 
> " I have an inner ground plane in an area with high voltage (to 600 V).
> My question is this: What is the recommended spacing between the
> plated-though hole with this voltage and the internal ground plane
> relief outline? I will go with 10 V/mil as a default, but I am hoping
> the safe limit might be a bit higher than this."
> 
> Can you point me to an IPC spec for this?  I was thinking it might be in
> 2222.
> 
> Thanks in advance.
> 
> Phil
> 
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