Long before lead-free solders came into widespread use, our esteemed forum contributor Werner Engelmaier wrote, "When surface mount solder joints connect materials with different CTEs, global thermal expansion mismatches result. Also, if the materials to which the solder bonds have CTEs different from the CTE of solder, local thermal expansion mismatches result. These thermal expansion mismatches are the cause of most SM solder joint failures." (ISBN 1-880433-16-8, September 1994)

In my experience with lead-free solders, I have found this statement holds true now more than ever.? Where tin-lead solder performed without failure in a control population, LF solder's stiffness, in layman's terms (the only ones I understand), resulted in components tearing right out of the solder fillet under conditions of high CTE mismatch in my thermal cycle test.

From my literature review, I have these CTE values for materials in a typical PCBA system:
??? CTE Copper? = 17-20 ppm/degree C
??? CTE LF solder = ~18 ppm/degree C
??? CTE Tin = 23 ppm/degree C
??? CTE TBBPA FR4 (X-Y) = ~18 ppm/degree C
??? CTE HF laminate (X-Y) = 10-13 ppm/degree C
??? CTE Alloy 42 = 4.5-6.5 ppm/degree C

Digging deeper, one could consider the CTEs of IC mold compounds, die, and die attach materials, but my brief research here has produced little solid information and widely varying CTE values.

My question is how much CTE mismatch can a PCBA be expected to withstand in a user environments of, say, (1) a lap top computer, (2) a desk top computer, and (3) an automobile, where one is warrantying the product for five years?? What rule of thumb can one use for CTE mismatch to engineer a reliable product?

Additionally, lacking such a design guide and/or requisite material information, presumably one would want to test his product with extensive thermal cycling, if Mr. Engelmaier's statement above still holds true.? Would someone please say again what the dwell time at extremes should be for lead-free solder systems in order to experience the full CTE hysteresis loop?

Many thanks in advance,

Bill Haas





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