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September 2007

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Subject:
From:
Ian Hanna <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Ian Hanna <[log in to unmask]>
Date:
Thu, 13 Sep 2007 13:59:36 -0400
Content-Type:
text/plain
Parts/Attachments:
text/plain (119 lines)
Mike -- are these cracks always associated with similar geography?
Looks like there is could be an association between the copper plane
layer topography and this defect -- the cracks appear in regions around
the thermals and knock-outs where there is a step down from copper to
bare laminate...is this always true?  could be stressing the copper --
anything unusual in the build/lay-up -- heavy copper, thin dielectrics,
brittle base material or low t&e of the foil?  My $.02 worth -- change,
no doubt, is inevitable -- ian



-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of John Burke
Sent: Thursday, September 13, 2007 12:58 PM
To: [log in to unmask]
Subject: Re: [TN] Inner trace defects post-fab/BBT

I am assuming that the close up shots are Z axis sections?

Which if they are, and those are indeed inner layers, the board is
showing
signs of unusual localized deformation since the "two halves" of the
break
are not aligned, and if this is indeed an inner layer section, they
should
be, broken or not.

Have you taken a look at the test fixture for the final board assembly?
You
can sometimes get very bad local board deformation due to uneven pusher
pin
distribution.

Kind regards

 
 
John Burke
 
(408) 515 4992

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Michael F Greaves
Sent: Thursday, September 13, 2007 8:11 AM
To: [log in to unmask]
Subject: Re: [TN] Inner trace defects post-fab/BBT

On 2007-09-13 08:01, Stadem, Richard D. wrote:
> Technet strips attachments.

Thanks everyone.  I was surprised to find an attachment
facility there on the post-message page.

I've just had them put on a web server:

http://tumladen.net/pcb/pic00041.jpg
http://tumladen.net/pcb/pic06334.jpg
http://tumladen.net/pcb/pic18467.jpg
http://tumladen.net/pcb/pic26500.jpg

> Has anyone experienced the defects illustrated in the 4
> attached images? We are confident that these were properly
> tested at bare-board electrical test, and that these apparent
> opens must have completely separated later.
> Assemblies show some failures due to high-R at these kinds of
> defects (this one was a complete open).  We don't believe
> they were visible at AOI, but are attempting to replicate
> them and verify this.  We are guessing that a foil weakness
> existed at lamination, but failure did not occur until
> subsequent thermal or mechanical stress during assembly or in
> the field.
>
> Anyone have any thoughts?  Thanks very much.

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