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Date: | Mon, 10 Sep 2007 14:36:15 -0700 |
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IPC Designers Council - Silicon Valley Chapter
Tuesday, Sept 11th, 2007
Time: 11:30AM - 1:30PM
Mentor Graphics
1001 Ridder Park Drive, San Jose, CA
Speaker: Mike Wilson (ADI / Cadplex Sales)
Topic: Tools for mixed EDA flows ( Cadence and Mentor )
Schematic symbol generation tool
Converting symbols
FPGA Bback-Annotation
Engineer FloorPlanning prior to PCB layout
Cross-probe from schematic to board
Accelerated Placement techniques
Design Re-Use modules for flat schematics
FPGA / Board Co-Design
Please RSVP to: [log in to unmask]
$1 for members; $5 for guests
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