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Date: | Thu, 13 Sep 2007 10:18:21 -0500 |
Content-Type: | text/plain |
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Yea, in a previous life in a PWB factory.
Poor Photo resist adhesion can cause this.
Inadequate Rinse or long period before rinse.
These type of anomalies play havoc on a timing circuit.
Final Test parameters can be made to pass such defects, low and Hi
impedance value settings.
Victor,
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Michael F Greaves
Sent: Thursday, September 13, 2007 10:11 AM
To: [log in to unmask]
Subject: Re: [TN] Inner trace defects post-fab/BBT
On 2007-09-13 08:01, Stadem, Richard D. wrote:
> Technet strips attachments.
Thanks everyone. I was surprised to find an attachment
facility there on the post-message page.
I've just had them put on a web server:
http://tumladen.net/pcb/pic00041.jpg
http://tumladen.net/pcb/pic06334.jpg
http://tumladen.net/pcb/pic18467.jpg
http://tumladen.net/pcb/pic26500.jpg
> Has anyone experienced the defects illustrated in the 4
> attached images? We are confident that these were properly
> tested at bare-board electrical test, and that these apparent
> opens must have completely separated later.
> Assemblies show some failures due to high-R at these kinds of
> defects (this one was a complete open). We don't believe
> they were visible at AOI, but are attempting to replicate
> them and verify this. We are guessing that a foil weakness
> existed at lamination, but failure did not occur until
> subsequent thermal or mechanical stress during assembly or in
> the field.
>
> Anyone have any thoughts? Thanks very much.
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