New IPC webcast series

Via Hole Filling Technology and Processes 

November 1 & 8, 2007 10:00 am - 11:00 am (CST)

Instructor:  Michael Carano, Electrochemicals, Inc.

 

The continued fast pace towards miniaturization is leading circuit board
designers to push the envelope on integration density. This trend is
driving fabricators to closely look at methods and processes that will
enable the move towards sequential lamination, blind and buried vias,
and via-in-pad technology.

 

The following topics will be covered on November 1, 2007:

 

* Introduction to via filling

* What is via filling

* Technology drivers for via filling 

* Different types of via structures 

* Overview of via filling processes

* Filling via polymer materials

* Filling via plating

* Via fill by electroplating

* Theoretical considerations

* Plating additive design

* Plating process parameters

* Plating cell design

* Reliability

* Troubleshooting 

 

The following topics will be covered on November 8, 2007:

 

* Introduction to via filling with polymer based materials 

* Why use polymer based materials 

* Conductive versus non-conductive via fills 

* Material considerations 

* Electrical/physical properties 

* Methods of via filling 

* Hand screening 

* Roller coating 

* Vacuum plugging equipment 

* Over metallization considerations 

* Troubleshooting 

 

Register by October 1, 2007, and save an additional 10% off.  To
register, please cut and paste www.ipc.org/ViaHoleWC  into your browser
and download the registration form.

 


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