To add to this, we will frequently route a slot between two traces or
pads to increase the creepage clearance when a large physical distance
is not possible.
For numbers we use 10 kV per inch for surface creepage and clearance in
air.
For boards submerged in dielectric oil we use 20 kV for surface creepage
and 50 kV for clearance in oil.
For hipot tests (4 kV) to satisfy medical requirements we use 8 mm
spacing between SELV and ground.
Conformal coating can help, but we typically don't need it.
Phil
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Hernefjord Ingemar
Sent: Friday, August 17, 2007 3:07 AM
To: [log in to unmask]
Subject: Re: [TN] Seeking design information on PWB conductor spacing
for high voltage (500-1000 VDC) applications
We have a rather simple thumb rule for top conductors:
flashover 1,250 VDC/mm for dry air
flashover 2,500 VDC/mm for solder mask
flashover 7,500 VDC/mm for potted board
to avoid creep current you need following distance between top
conductors:
7 mm/kV up to 3,000 meter altitude without protection, clean air
15 mm/kV up to 3,000 meter " " " , dusty air
25 mm/kV up to >3,000 meter " " " , std environment
5 mm/kV up to 3,000 meter " with protection, std environment
2.5 mm/kV up to >3,000 meter " " " "
We make MIL products, UL and other commercial requirements are of course
different.
The cleanliness of the boards is mainly the deciding basis for the
isolation distances.
This information is based on rather old stuff, but I think not much is
changed.
Inge
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Gerald Bogert
Sent: den 17 augusti 2007 00:24
To: [log in to unmask]
Subject: [TN] Seeking design information on PWB conductor spacing for
high voltage (500-1000 VDC) applications
August 16, 2007
IPC-2221 section 6.3 and the associated table provides specific
electrical conductor spacing requirements for voltages up to 500 volts.
However, for voltages > 500 volts, it defaults to a formula in section
6.3.
What is the technical basis for the minimum spacing requirements that
are
listed in the table? How reliable is the formula for voltages > 500
volts.
How valid is the formula if we have 1000 VDC on the PWB?
Since the table does not specifically list minimum electrical spacing
for voltages > 500 volts is the formula just a "SWAG" or based on real
data? If so, what is the formula based on?
Does anyone have design standards for high voltage PWB spacings that
they are willing to share?
We had an OEM that had recent field failures (shorts to internal traces)
of a conformal coated multilayer FR4 PWB (0.062 in) that has both low
(logic
voltage) and high (approx 780 VDC nominal) circuits. The board was
required to be designed to IPC-D-275 requirements, and the table in 275
is basically the same as in IPC-2221.
The PWB is being redesigned and I need to verify the new design meets
reliable and valid minimum conductor spacing requirements. Are there
any design standards other than IPC-2221 that could be used for high
voltage PWB?
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